We would like to remove the 33.33333 MHz oscillator to the Zynq and replace it with a better, pin compatible 40MHz oscillator. We've done the rework and the device boots up and we're getting the FPGA done light.
What I've noticed is that the UART clock now seems off, we're getting giberish on UART1 and ethernet no longer works. I presume the issue is that the FSBL and Linux don't know that the oscillator has chganged so something is messed up w/ the PLLs used to generate the baud and ethernet clocks.
I used the Zynq PS IP block to update the clock frequency to 40MHz, this in turn updated all of the dividers in the GUI. I re-generated the bitstream, exported to SDK to rebuild the FSBL, and re-imported the HDF file in petalinux and I am seeing the same problem. Checking the newly generated device tree shows 40MHz as the new clock frequency.
Did I miss a step somewhere? Do I need to update something else, besides the PS configuration? Attached is a screenshot of the PS configuration.
