In the PicoZed PCIe FMC carrier reference design (both V1 and V2), the ADP5052 PWRGD signal is being used as PG_MODULE to signal the Zynq to boot.
From what I can tell from the ADP5052 datasheet, the PWRGD signal is asserted as soon as the channel 1 supply is "good". It doesn't monitor channels 2-4 unless you special order a custom version of the ADP5052, and 5 cannot be monitored.
In V1 of the carrier card, Channel 1 is used for the 1.0V supply, and it is enabled first. I believe that means that the Zynq will start booting up before the other supplies (1.2, 1.8, 3.3) have come up (probably not by much, but technically still before).
In V2 of the carrier card, the channels are used in a different order such that Channel 1 and 2 are the last to come up.
Is my understanding of that schematic change correct? I think that change makes PG_MODULE more correct, in that it won't try to boot the Zynq too early.
Thanks for any insight!