Actions
Forum Thread Details
  • State Verified Answer
  • Replies 3 replies
  • Subscribers 338 subscribers
  • Views 1279 views
  • Users 0 members are here
Related

changes to IBERT example break PLL lock

Dillon1337

I have the FMC Carrier Card rev C03 and the pz030 SOM. I can generate the example project at https://github.com/Avnet/hdl/tree/master/Projects/ibert and the PLL locks and has correct data rate. But if I change anything in the project, the PLL no longer locks. For example, in the example generated, I can open the IP block and change the data rate from 6.25 gbps to 2.0 gbps (keeping everything else the same - refclk at 250mhz, protocol and clock using refclk1) and after it builds, the PLL will not lock in the IBERT tool. I've tried TONS of combinations but nothing but the default settings will let the PLL lock. Is there an explanation for this? What am I doing wrong/not understanding?

Thanks in advance!

Dillon

Parents
  • 0

    Hi there,

    What version of Vivado are you using?
    What design document are you using?
    Are you actually using TIP (per your link) or are you using a tag?  If a tag, which one?
    Are you using an I grade or C grade PicoZed?

    IN the mean time, take a look a the wizard as you change things.  Generally speaking, there are limits to what the combination of values can be and each field has a relationship to other fields.  That is, depending on what frequency you CHOOSE, you might have to change to a CPLL instead of the QPLL.  It also might help if you change the frequency of the incoming clock as PLLS take that frequency, multiply that, then divide back down.  The type of PLL might not allow for a division from 250MHz to the 2.0gbps you are requesting.

    If that is the case, It seems you have a V1 carrier card.  You will need to change the clock using the Carrier Card manual instructions.

    If you have a V2, use the clock programming example located on the PicoZed.org website to change the  clock configuration to one that Vivado states you can use for your 2.0gbps design.  Due to the quality of the IDT part, I would suggest something as high in value as allowed, that will help reduce the jitter induced by the transceiver PLL.

    --Dan

Reply
  • 0

    Hi there,

    What version of Vivado are you using?
    What design document are you using?
    Are you actually using TIP (per your link) or are you using a tag?  If a tag, which one?
    Are you using an I grade or C grade PicoZed?

    IN the mean time, take a look a the wizard as you change things.  Generally speaking, there are limits to what the combination of values can be and each field has a relationship to other fields.  That is, depending on what frequency you CHOOSE, you might have to change to a CPLL instead of the QPLL.  It also might help if you change the frequency of the incoming clock as PLLS take that frequency, multiply that, then divide back down.  The type of PLL might not allow for a division from 250MHz to the 2.0gbps you are requesting.

    If that is the case, It seems you have a V1 carrier card.  You will need to change the clock using the Carrier Card manual instructions.

    If you have a V2, use the clock programming example located on the PicoZed.org website to change the  clock configuration to one that Vivado states you can use for your 2.0gbps design.  Due to the quality of the IDT part, I would suggest something as high in value as allowed, that will help reduce the jitter induced by the transceiver PLL.

    --Dan

Children
No Data