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changes to IBERT example break PLL lock

Dillon1337

I have the FMC Carrier Card rev C03 and the pz030 SOM. I can generate the example project at https://github.com/Avnet/hdl/tree/master/Projects/ibert and the PLL locks and has correct data rate. But if I change anything in the project, the PLL no longer locks. For example, in the example generated, I can open the IP block and change the data rate from 6.25 gbps to 2.0 gbps (keeping everything else the same - refclk at 250mhz, protocol and clock using refclk1) and after it builds, the PLL will not lock in the IBERT tool. I've tried TONS of combinations but nothing but the default settings will let the PLL lock. Is there an explanation for this? What am I doing wrong/not understanding?

Thanks in advance!

Dillon

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    Vivado: 2016.4

    design document: Vivado 2015.2 Version for PicoZed 7030 + PicoZed FMC1 Carrier Card. located at the bottom of http://zedboard.org/support/design/4701/76

    git: I checked out commit 6f1cea4. But I have the same behavior if I create the project from scratch from the procedure in the above design document.

    temp: C grade

    As far as hardware, I'm only using the PCIe loopback adapter to connect 1 out of the 4 links

    According to the equation 2-3 and 2-4 in UG476, I should be able to use the quad PLL with 250Mhz to operate at a 2Gbps rate (using N=16, M=1, D=2 for instance).

    I do have the V1 card and know how to change the clock.

     

    I've tried to use "known good" settings in ug476 table 2-17 and they don't lock either. For instance, the PCIe should run with100Mhz ref clock to 8Gbps but the IP tool won't allow me to set the rate higher than 6.6Gbps (which is the limit of the CPLL and I"m selecting Quad PLL, so I'm wondering if the tool is incorrect?)

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    Vivado: 2016.4

    design document: Vivado 2015.2 Version for PicoZed 7030 + PicoZed FMC1 Carrier Card. located at the bottom of http://zedboard.org/support/design/4701/76

    git: I checked out commit 6f1cea4. But I have the same behavior if I create the project from scratch from the procedure in the above design document.

    temp: C grade

    As far as hardware, I'm only using the PCIe loopback adapter to connect 1 out of the 4 links

    According to the equation 2-3 and 2-4 in UG476, I should be able to use the quad PLL with 250Mhz to operate at a 2Gbps rate (using N=16, M=1, D=2 for instance).

    I do have the V1 card and know how to change the clock.

     

    I've tried to use "known good" settings in ug476 table 2-17 and they don't lock either. For instance, the PCIe should run with100Mhz ref clock to 8Gbps but the IP tool won't allow me to set the rate higher than 6.6Gbps (which is the limit of the CPLL and I"m selecting Quad PLL, so I'm wondering if the tool is incorrect?)

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