If you are designing a PicoZed Carrier that supports either the PicoZed 7015 or 7030, you must design for the transceivers. What if you aren't using the transceivers in your design? How should the Rx, Tx, Clocks, and power pins be handled? The best references for this are: Xilinx UG476 (Table 5-7: GTX/GTH Transceiver PCB Design Checklist , in 14 Aug 2018 version) for the PicoZed 7030 Xilinx UG482 (Table 5-4: Unused GTP Quad Column Connections , in 19 Dec 2016 version) for the PicoZed 7015 https://forums.xilinx.com/t5/7-Series-FPGAs/Kintex-7Gtx-transceiver-connections/m-p/694453/highlight/true#M16395 I will summarize in the table below. Pins Recommendations Where Handled MGTREFCLK* Float Carrier -- up to the user MGTXRX*, MGTHRX* GND Carrier -- up to the user MGTXTX*, MGTHTX* Float Carrier -- up to the user MGTAVCC GND Carrier -- up to the user MGTAVTT GND Carrier -- up to the user MGTVCCAUX VCCAUX SOM -- connected to filtered 1.8V Bryan

Unused MGT -- how to handle on PicoZed Carrier

If you are designing a PicoZed Carrier that supports either the PicoZed 7015 or 7030, you must design for the transceivers. What if you aren't using the transceivers in your design? How should the Rx, Tx, Clocks, and power pins be handled?

The best references for this are:

Xilinx UG476 (Table 5-7: GTX/GTH Transceiver PCB Design Checklist, in 14 Aug 2018 version) for the PicoZed 7030
Xilinx UG482 (Table 5-4: Unused GTP Quad Column Connections, in 19 Dec 2016 version) for the PicoZed 7015
https://forums.xilinx.com/t5/7-Series-FPGAs/Kintex-7Gtx-transceiver-connections/m-p/694453/highlight/true#M16395

I will summarize in the table below.

Pins	Recommendations	Where Handled
MGTREFCLK*	Float	Carrier -- up to the user
MGTXRX, MGTHRX	GND	Carrier -- up to the user
MGTXTX, MGTHTX	Float	Carrier -- up to the user
MGTAVCC	GND	Carrier -- up to the user
MGTAVTT	GND	Carrier -- up to the user
MGTVCCAUX	VCCAUX	SOM -- connected to filtered 1.8V

Bryan