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Can't boot from eMMC in Standard Speed Mode at -30degC

Former Member

At -15degC its ok but it needs to boot at -30degC.

I have at least 2 rev C Picozed 7030's with this problem and have complied with the advisory note by operating in standard speed mode at 25MHz (section 3.7 in the Avnet Errata).  Signal eMMC_CLK has been measured at 25MHz to verify this.

Do I have faulty boards, or is there anything else I've overlooked ?

I can provide screen dumps from the serial port or other information as required.

Please advise.

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    Hi robertdf,

    Thank you for the feedback on this!

    Yes, since it is open source code you are modifying and subject to change by the community at any point, it is very likely that the code changes will not line up line for line with the changes we prescribe for 2015.4 source code snapshots.  It sounds like they are close enough that the differences were not too difficult to translate so that is some good news, thank you again!

    Yes, if you read PCN you can see that the multiplexer on the SDIO interface was removed to improve the timing budget and there is not an easy way to document the timing budget analysis without risk of making the multiplexer look like a bad part.

    The multiplexer is in fact not a bad part, it simply was not the best choice for an eMMC interface running at 50MHz across temperature range with a single clock driving the round trip timing budget for SDIO transactions.  For the purpose of restoring the higher value feature (the 50MHz eMMC operation) on all boards with the only tradeoff being the lack of dynamically selecting between SDIO and GPIO functions for those MIO pins, the tough design decision was made to remove the Mux for Rev. E and maximize the timing budget across for the SDIO interface across operating temperature range so that reliability can be achieved for all PicoZed flavors 7010/7015/7020/7030.

    Likewise, the software fix for Rev. C and earlier does improve the timing budget by decreasing the clock frequency and changing the clock edge upon which the data is latched against.

    I cross linked this thread against the Xilinx thread which has additional info that may be useful to others that stumble across this legacy feature in the future:

    https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-SDIO-max-clock-speed/td-p/861548

    Also note that Rev. E eMMC hardware is upgraded from v4.41 4GB to v5.0 8GB MTFC8GAKAJCN-4M IT devices.

    Best Regards,

    -Kevin

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  • 0

    Hi robertdf,

    Thank you for the feedback on this!

    Yes, since it is open source code you are modifying and subject to change by the community at any point, it is very likely that the code changes will not line up line for line with the changes we prescribe for 2015.4 source code snapshots.  It sounds like they are close enough that the differences were not too difficult to translate so that is some good news, thank you again!

    Yes, if you read PCN you can see that the multiplexer on the SDIO interface was removed to improve the timing budget and there is not an easy way to document the timing budget analysis without risk of making the multiplexer look like a bad part.

    The multiplexer is in fact not a bad part, it simply was not the best choice for an eMMC interface running at 50MHz across temperature range with a single clock driving the round trip timing budget for SDIO transactions.  For the purpose of restoring the higher value feature (the 50MHz eMMC operation) on all boards with the only tradeoff being the lack of dynamically selecting between SDIO and GPIO functions for those MIO pins, the tough design decision was made to remove the Mux for Rev. E and maximize the timing budget across for the SDIO interface across operating temperature range so that reliability can be achieved for all PicoZed flavors 7010/7015/7020/7030.

    Likewise, the software fix for Rev. C and earlier does improve the timing budget by decreasing the clock frequency and changing the clock edge upon which the data is latched against.

    I cross linked this thread against the Xilinx thread which has additional info that may be useful to others that stumble across this legacy feature in the future:

    https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Zynq-SDIO-max-clock-speed/td-p/861548

    Also note that Rev. E eMMC hardware is upgraded from v4.41 4GB to v5.0 8GB MTFC8GAKAJCN-4M IT devices.

    Best Regards,

    -Kevin

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