Clock in FMC connector

Question

Dear all,

I'm new with the PicoZed 7030 Carrier Card V2.

I would like to output a single-ended 100 MHz clock from the FMC connector.

I used clock wizard (MMCM).

CLKIN->processing_system7_0::FCLK_CLK0
CLKOUT0->clk_out1

I used the following constraints:

set_property PACKAGE_PIN G3 [get_ports clk_out1];

set_property IOSTANDARD LVCMOS18 [get_ports clk_out1];

I was expecting to see a clock on the FMC connector at pin H7. However I don't see any signal.

Can you please help me? Which pin I should use on FMC connector and how should be the constraints?

Can I send directly FCLK_CLK0 (100 MHz) from the FMC connector?

Thank you very much in advance.

Best Regards,

Marco

drozwood90 · Accepted Answer

Hi there,

First, if you are seeing 5V on bank 35 with a PicoZed 7030, it is possible that you have damaged the chip. The bank voltage for the PicoZed 7030 is 1.8V across the board. That is clearly written in the setup guides as well as in the silk screen on the board. Please check that you have configured the bank voltage jumpers for 1.8V (default). Depending on pin configuration, if you are seeing ring on the signal, I would not expect it to be more than 1-1.5V for a VERY short time. I would also suggest double checking the voltage division multiplier for the scale on your scope, just to rule out the simple things!

Next, measuring a clock at those speeds is highly dependent on your setup. Just because your scope has a 1GHz bandwidth, does not mean that it can accurately see a 100MHz clock as it depends on your probes as well as the signal strength of what you are measuring. From experience, I also know that measuring a signal with a scope that has 2.5GHz bandwidth vs 10GHz bandwidth, there is a VERY noticeable difference to the look of the sampled signal. The 10Ghz looked more square.

Next, probes typically have a capacitive filter and a multiplier with calibration on its front end. Usually the filter / multiplier is stepped and usually only 1 set frequency and voltage division. 50MHz, 100MHz, 150MHz. This will cause the signal to degrade as you close in or superseded those frequencies as per any sampling theory when looking at the effects of filtering / adding impedance (be it L, C, or R - which the higher in frequency you go, the more you need to look at these components as Z or impedance). I would recommend an ACTIVE probe as that will get you the BEST look as they are typically VERY high impedance and can typically be used to measure MOST high-speed sensitive signals.

Next, as you get higher in speed, your GROUND placement is critical. If you choose a ground at the provided power supply ground point on the FMCv2 Carrier Card, you will likely get noise and other issues with your signal. You will want to use a ground that is ON the FMC connector. I'm not sure HOW you are probing the connector pin, but you should choose a ground that is as close to the pin of interest as possible. For instance, to look at the IDT clock's signals, there are grounds and sampling pads VERY close to the IDT Universal Frequency Translator chip itself.

Next, I'm not sure why you need a very sharp square edge. Is there something about your circuit that needs that? Any device that I can think of is not edge sensitive, but level sensitive. I am sure there might be something out there, however due to the capacitive and inductive nature of copper over frequency (especially as you approach 1GHz), the "squareness" typically goes away and typically ends up with some rounded look - or as you put it, sine look. As the pins of the FPGA are really designed for function, not look, I do not think you are going to get what you are looking for with an FPGA pin, especially a NON-clock capable pin (which E4 is not a CLOCK capable pin). It is the positive side of the LVDS pair E4/E3. A clock capable pin will have much better response as it is specifically designed to handle clocks. More-so as an input as you have greater access to the clocking trees (MRCC are multi-region and SRCC is single region as per UG475).

Next, as circuits are typically level sensitive, you can just pick a point on the clock, then measure periods, or any other measurement using that point as the start point. You will see with a feature enabled like infinite persistence that triggering your scope at that point will produce very repeatable results - which in a clock is ultimately the MOST important thing (low jitter, with reproducible toggling).

Lastly, if you are really worried about having a clean and sharp clock, I would suggest you NOT use the clock from the PS. It is a good clock, but it is just a normal clock. In range of performance for the Zynq-zc7030, I would order the PLLS:
*PS clocks
*PL MMCM (although VERY flexible)
*PL PLL (higher performance, at the expense of flexibility)
*MGT CPLL (more tuned for PCIe and multiples similar in clock rate)
*MGT QPLL (highest performance)

Using the external IDT clock that is included on the FMCv2 Carrier Card will get you a very high quality clock and can be used to drive clocks out to the FMC port as well as the FPGA itself (using the MGTREFCLK input). This clock will easily produce a square wave, however again, as you measure it, that will change the clock's wave. That is, unless you minimize the affect of your probe, such as using an active probe.

I hope the above explains why I cannot really answer your question. If you need a VERY square clock, then I think you need to evaluate how you are measuring the output of the pins - then tune your FPGA pins or use the clock from the IDT chip. It becomes VERY subjective depending on how you are measuring.

Also, to comment on your comment of the PL PMOD connector. The PMOD connectors have a specification to be rated to 100MHz. The FMC connector is rated much higher. Your best bet to get the BEST clock squareness is from that connector and use differential as that eliminates board noise issues, but as I said, measuring it can drastically change the waveform and traditionally the squareness of said clock does not typically matter. That is where the SETUP and HOLD times of your constraints/design come into play. It ensures that there is ample time for the signal to traverse from LOW-TO-HIGH or HIGH-TO-LOW with the HOLD time giving the "peak" or "trough/valley" enough time to be high/low for sampling by the rest of the circuit. That is why there is almost always a timing diagram in any chip that is supposed to be attached to something else through a bus (such as an ADC/DAC) - allowing the designer to tell Vivado the timing tolerances, allowing the fabric to be routed in such a way to meet that timing.

--Dan