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IDT Programming Using Avnet Reference Design

nima_taie

I am following Avnet reference design from Github to change the frequency of the U13 which is IDT 8T49N242. Everything goes OK, and I get the message IIC EEPROM Test: PASSED message at the end, however, after I power cycle, I still don’t have new clock frequency from the IDT device.

The reference design is programming the EEPROM which is U14, and it is at address 0xA0. However, the  slave address which is indicated in the pzcc_iic_eeprom_test.c source file is at 0x50. I tried to change it to 0xA0, but then the EEROM test fails. After programming the EEPROM, is there anything else I need to do? Why am I not getting the frequency which I want?

I am using Vivado 2015.4 as the reference design requires.

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    Hi Dan,

    Let me give you more background on what I am trying to do with the Picozed, and V2 Carrier Board. 

    I am using Picozed board as a PCIe root complex - however, the carrier board is designed to be an end-point PCIe for Picozed. The PCIe REFCLK on PCIe edge are inputs to the IDT and FPGA high speed transceivers. I need to provide a reference clock to both FPGA pins, and also PCIe Edge connector. 

    I was hoping to use the output from IDT device to provide a clock to both FPGA and PCIe. I wanted to route TP33/34 or TP35/36 to the pads of R106 after removing R106. The reason for removing it was that PCIe end point devices has the 50Ohm termination. 

    I see your point in using different clock values at output of Q0-Q2. However, I don't see any activity. Not even a glitch. I have also changed the output type from HCSL to LVDS, but still no activity. 

    I noticed on IDT's data sheet for the clock device, Q0 and Q1 are using CLK0 and CLK1 as reference inputs. I don't have CLK0 and CLK1, but I have changed their input source using Timing Commander to be Q3 rather than Q0 in the PLL section. 

    Anyway, I am planning to go off-board to a PCIe end-point device hence the need to for HCSL output. 

    What is your recommendation for PCIe REF Clk then? I need to pair of clocks for FPGA MGTs, and one pair for PCIe reference clock on edge? 

    Thanks,

    Nima

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  • 0

    Hi Dan,

    Let me give you more background on what I am trying to do with the Picozed, and V2 Carrier Board. 

    I am using Picozed board as a PCIe root complex - however, the carrier board is designed to be an end-point PCIe for Picozed. The PCIe REFCLK on PCIe edge are inputs to the IDT and FPGA high speed transceivers. I need to provide a reference clock to both FPGA pins, and also PCIe Edge connector. 

    I was hoping to use the output from IDT device to provide a clock to both FPGA and PCIe. I wanted to route TP33/34 or TP35/36 to the pads of R106 after removing R106. The reason for removing it was that PCIe end point devices has the 50Ohm termination. 

    I see your point in using different clock values at output of Q0-Q2. However, I don't see any activity. Not even a glitch. I have also changed the output type from HCSL to LVDS, but still no activity. 

    I noticed on IDT's data sheet for the clock device, Q0 and Q1 are using CLK0 and CLK1 as reference inputs. I don't have CLK0 and CLK1, but I have changed their input source using Timing Commander to be Q3 rather than Q0 in the PLL section. 

    Anyway, I am planning to go off-board to a PCIe end-point device hence the need to for HCSL output. 

    What is your recommendation for PCIe REF Clk then? I need to pair of clocks for FPGA MGTs, and one pair for PCIe reference clock on edge? 

    Thanks,

    Nima

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