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IDT Programming Using Avnet Reference Design

nima_taie

I am following Avnet reference design from Github to change the frequency of the U13 which is IDT 8T49N242. Everything goes OK, and I get the message IIC EEPROM Test: PASSED message at the end, however, after I power cycle, I still don’t have new clock frequency from the IDT device.

The reference design is programming the EEPROM which is U14, and it is at address 0xA0. However, the  slave address which is indicated in the pzcc_iic_eeprom_test.c source file is at 0x50. I tried to change it to 0xA0, but then the EEROM test fails. After programming the EEPROM, is there anything else I need to do? Why am I not getting the frequency which I want?

I am using Vivado 2015.4 as the reference design requires.

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    Nima,
    Please let me know how your experiment works. It sounds like you are covering a lot of the troubleshooting tips I would have provided!

    Can you tell me what your source clock is?
    Are you using the 38.88MHz crystal input?
    Are you using the FMC or PCIe path for feeding a clock in?
    Do you have access to a way to put a clock on one of those paths?
    If so, you would be able to also test the two included BIN files that configures the part as a MUX, which would show that the part is behaving as expected.

    Are all Q0-Q2 clocks setup for the same value, or are you using different values for each? I have used some of the lines connected to the Test Points to produce varying clocks, just to validate that I am seeing other programming configurations.

    Since you indicated you are using HCSL, are you feeding these clocks off board somehow?
    HCSL requires 50ohm to ground. Please see: IDT's AN808 It coveres most of the situations that you would need to account for.  https://www.idt.com/document/apn/808-pci-expresshcsl-termination

    The PicoZed 7030 has 100Ohm termination at the Zynq part for the MGT inputs (see sheet 4, R91, in the "PicoZed 7015/7030 Schematics Rev C.04" located http://picozed.org/support/documentation/4736) and is AC coupled.  That could pose a problem as we have not run the clock with HCSL.  We have used LVPECL and LVDS.  If you need HCSL, you might need to change the circuitry depending on what you are attaching to the FMCv2.  If you are staying onboard, I would suggest you use LVPECL or LVDS.

    --Dan

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  • 0

    Nima,
    Please let me know how your experiment works. It sounds like you are covering a lot of the troubleshooting tips I would have provided!

    Can you tell me what your source clock is?
    Are you using the 38.88MHz crystal input?
    Are you using the FMC or PCIe path for feeding a clock in?
    Do you have access to a way to put a clock on one of those paths?
    If so, you would be able to also test the two included BIN files that configures the part as a MUX, which would show that the part is behaving as expected.

    Are all Q0-Q2 clocks setup for the same value, or are you using different values for each? I have used some of the lines connected to the Test Points to produce varying clocks, just to validate that I am seeing other programming configurations.

    Since you indicated you are using HCSL, are you feeding these clocks off board somehow?
    HCSL requires 50ohm to ground. Please see: IDT's AN808 It coveres most of the situations that you would need to account for.  https://www.idt.com/document/apn/808-pci-expresshcsl-termination

    The PicoZed 7030 has 100Ohm termination at the Zynq part for the MGT inputs (see sheet 4, R91, in the "PicoZed 7015/7030 Schematics Rev C.04" located http://picozed.org/support/documentation/4736) and is AC coupled.  That could pose a problem as we have not run the clock with HCSL.  We have used LVPECL and LVDS.  If you need HCSL, you might need to change the circuitry depending on what you are attaching to the FMCv2.  If you are staying onboard, I would suggest you use LVPECL or LVDS.

    --Dan

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