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Can I use a PicoZed V2 Carrier as a root complex?

eg0n

I have a project where I want to experiment with a root complex design, but I only have a PicoZed 7015 SOM and V2 Carrier. Is it possible to put a root complex design on a PicoZed SOM and connect a PCIe endpoint with a female-female cable to the V2 Carrier card? Is there anything electrically wrong with that other than the lack of power rails provided to the second endpoint, or is that just impossible? I can look at getting the mini ITX board, but I'd rather use the equipment I have already if possible. Thanks!

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  • 0 in reply to clem57

    But I see:

     

             2.9          Multi-Gigabit Transceivers(MGTs)

    PicoZed 7015/7030 has four gigabit full-duplex transceiver lanesthat reside on Bank 112 of the Zynq device.

    These high speed transceivers can be used to interface to multiple high speed interface protocols such as PCI Express, Ethernet, Serial ATA and more.The XC7Z015-1CLG484is enabled with GTPtransceivers which are capable of a transceiver data rate up to 3.75Gb/s.

    Speed grade devices of -2 or -3 are capable of data transceiver rates up to 6.25Gb/s.

    The Xilinx XC7Z030-1SBG485is enabled with GTX transceivers which are capable of a transceiver data rateup to 6.6Gb/s.

    Speed grade devices of -2 or -3 are also capable of data transceiver rates up to 6.6Gb/s in the SB package.

    Two differential MGT reference clock inputs are available for use with the GTP/GTX lanes.

    Either clock input can be used as the clock reference for any one or more of the GT lanes in bank 112. This allows the user to implement various protocols requiring different line rates.

    Gigabit transceiver lanes and their associated reference clocks are connected to the carrier board via the JX3 Micro Header.The table below shows the connections between the Zynq device and the JX Micro Header.

    But will warn you that this is complex. Have you experience working with this board? If not set simple goals to learn from and build up to your final goal.

  • 0 in reply to clem57

    Oh awesome, that fpgadeveloper.com tutorial does indeed indicate I can do what I want to do. I do have experience building a PCIe endpoint with this board so it shouldn't be too much of a stretch. Thanks!

  • 0 in reply to eg0n

    Glad I can help. Please mark which post is more "Correct". Thanks.