IP not updating

Question

I am using Vivado 2015.2.1, Windows environment and Picozed hdl-2015_r2 pzsdr ccfmc project. When I "Edit in IP packager" axi_ad9361 it opens a .tmp project. I then make modifications to the IP and "Run Synthesis" OK. The Package IP does not reflect the changes or give me the option of updating. If I "Open Elaborated Design" the schematic opens and all of my changes are their. I get the flowing 48 warnings:

File groups 'xilinx_anylanguagesynthisis (Synthisis): "C:/PZ_5/hdl-2015_r2/Library/common/ad_mul.v" file path is not relative to root directory.

I do not know if these warnings are the reason for not letting me update the IP.

I looked at AR# 56102 to see about fixing the warning but this project hdl-2015_r2 pzsdr ccfmc is supposed to be a functioning project and I do not know if this is causing the problem with not being able to update the IP. It may be something else I am not doing. Vivado is a very puck puck puck intensive, to make any thing happen. Please help!!

Former Member · Accepted Answer

Instead of modifying IP in Vivado, it may be simpler to edit the source code directly in the Verilog .v files provided from Analog Devices GIT archive. You may then rebuild the IP libraries and entire Vivado project using the Analog Devices provided makefiles with the Linux-based ‘make’ utility, as documented in 'Appendix A: Building the PicoZed SDR Getting Started Design' http://picozed.org/sites/default/files/documentations/PicoZed%20SDR%20Development%20Kit%20Getting%20Started%20Guide%20v1.4_0.pdf . This method will preserve the dependencies in the build process for Vivado projects. For a complete description of the methodology used to build Analog Devices reference designs for Xilinx platforms, it is recommended to review the ADI Reference Designs HDL User Guide. http://wiki.analog.com/resources/fpga/docs/hdl