I'm confused about pin MIO[8] on the PZSDR 2x2 SOM.
The Zynq TRM v1.11 QPSI clock feedback section says (pg 353):
This pin is used with the high speed Quad-SPI timing mode, where the memory interface clock needs to be greater than 40 MHz. The feedback signal is received from the internal input from the I/O so MIO pin 8 needs to be programmed and allowed to freely toggle. ... When Quad-SPI feedback mode is used, the qspi_sclk_fb_out pin should only be connected to a pull-up or pull-down resistor which is needed to set the MIO voltage mode (vmode).
The PZSDR User Guide v1.7 QPSI section (pg 20) matches the TRM description for using MIO[8].
In the PZSDR schematics Zynq pin MIO[8]/A24 is pulled up to 1.8v and tied to the ETH0 PHY reset pin. I understand the pullup sets VMODE and helpfully clears the Eth PHY reset for designs that don't drive the reset signal.
However I'm confused how this relates to the QSPI use of MIO[8]. Does enabling the QPSI feedback clock (required for 40+MHz operation) result in MIO[8] toggling? Wouldn't this continuously reset/un-reset the ETH0 PHY?
Related, there's an inconsistency in the PZSDR User Guide Ethernet PHY Pinout (Table 7, pg 25). The table says ETH_RST_N is connected to Zynq pin A24 (matching the schematics) and to MIO[47]. However MIO[47] is connected to JX4.94 in the schematics.
