A couple of questions about the PZSDR FMC carrier Ethernet PHY reset.
The PZSDR FMC carrier drives the Ethernet PHY RESETN signal from a SN74LVC1G08 (2-bit AND) at U10 powered by 3.3v. The AND inputs are PG_MODULE (through an RC filter) and ETH1_RESETN. PG_MODULE is pulled up to VIN (nominally 5v) by the PZSDR SOM. The SN74LVC1G08 permits Vin up to 5.5v, so this seems ok. ETH1_RESETN is driven by the SOM at JX4.100. On the SOM JX4.100 is tied to Zynq pin B20 / MIO[51] in bank 501 with VDDO=1.8v.
Doesn't the 3.3v output of the SN74LVC1G08 exceed the absolute max voltage for the Marvell 88E1512 RESETN pin? The datasheet lists abs max of VDDO+0.7 for pins powered by VDDO; I think this includes RESETN.
The Zynq MIO[51] signal at 1.8v is below V_IH(min)=2.0v for the SN74LVC1G08 when VCC=3.3v. How does the Zynq reliably de-assert reset for the carrier's Eth PHY?