Many applications call for synchronized multiple RF inputs/outputs (MIMO), including phase array processing, beamforming, adaptive antennas, etc.
As described in http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync, there are (2) aspects to synchronizing multiple AD9361u2019s across PicoZed SDR SOMs.
u2022tSample clock Synchronization
otEach AD9361 includes its own baseband PLL that generates sampling and data clocks from the reference clock input. A logical SYNC_IN pulse input is needed to align each deviceu2019s data clock with a common reference. On PicoZed 7035/AD9361 SOM, the AD9361 'SYNC_IN' (pin H5) is connected to / driven from Z7035 IO_L10_35_SYNC_IN (pin G15).
u2022tRF (LO) Synchronization
otThe AD9361 does not include RF synchronization internally. Techniques to resolve phase difference of the RF PLLs across different AD9361 are discussed in http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync.
At this time the PicoZed SDR FMC carrier card is not intended to have more than one SOM. Therefore there is no (simple) connection to drive a common SYNC_IN to multiple SOMs / AD9361. Future PicoZed SDR carriers may provide such functionality.
It might be possible to drive a replica of u2018SYNC_INu2019 from the Zynq down through a custom PMOD output on a u2018masteru2019 carrier, then over a custom cable to a PMOD input of a u2018slaveu2019 carrier, and finally from Zynq to the u2018slaveu2019 AD9361 SYNC_IN. Skew would need to be somehow matched across the master / slave SYNC_IN signals. However, this isnu2019t a use case that we have specifically planned for. The user would need to do some experimentation.
