As my FPGA design is growing larger, I am starting to experience some automatic power-cutoffs using the latest firmware v1.4 for the ADM1166. Since I am getting varying power-cutoff behavior depending on the PL image I use for testing, it appears that the FW is not extensively characterized for all possible PL design variations and there is a risk that any design change I make to the PL could result in ADM1166 power-cutoffs.
I would like to know how important it is to monitor the supply voltages and automatically cut off power if any are out of spec? Is the goal to protect data in non-volatile memory in case of under/over voltage condition? Or is a power down sequence necessary to prevent permanent physical damage?
I ask because I am considering making a change to the ADM1166 FW v1.4 to modify that design to never cut off power even if a fault is detected. That way I can make PL changes without having to re-characterize the ADM1166 operation. But I would like to know the full consequences first before I make such a decision.
Thanks in advance for your help,