Hi, nice to meet you everyone.
Within a University Research Project, I'm working on a PicoZed SDR platform (PicoZed+PicoZed SDR) to implement a full duplex SDR able to communicate with some RFID-like tags.
The communication paradigm is quite simple: the SDR shall modulate an 5.8GHz RF carrier through an ASK modulation scheme (simply putting MIN_DAC,MAX_DAC values on the sample input port), and after that during a MAX_DAC interval belonging to a full continuous wave period such wave will be used by the tag to modulate its data through a switching diode.
The radio works almost all the time.
The problem is that sometimes, at the power-up and after the PLL is locked (that's verified through the AD9364 SPI registers state), the 9364 seems to totally ignore the sample stream which I send synchronous with the DATA_CLK and TX_FRAME signals. Looking through a spectrum analyzer, the PLL seems to be well-locked, but the carrier level is the same as when I put a flow of all zeros as samples: changing samples does not change anything.
When this happens, the radio must be switched off, resetted and restarted to restore the full functionality. This way, the "zero" RF carrier level is the same as in radio-stuck case, while the "one" RF carrier level belongs to the maximal output power.
I'm using Vivado 2017.3.1, and all the timing constraints are met. Also verifying through the oscilloscope, the samples are correctly sent both when the radio started well or not.
Actually I put a workaround making the radio resetting itself until a valid tag answer is obtained, but I would not apply such scheme in the final implemented product.
Have you any idea?