RFSoC ZCU208 HDL Coder Support in MATLAB/Simulink

Hi there, not sure but the zcu208 plug in code is partly installed with RFSoC Explorer, then you need to run the install m file (included in the extra zcu208 zip file per the instructions), which adds the zcu208 plug in code in rfsoc explorer into the Matlab path.  Then the zcu208 option can be selected for a new project.

The included examples for the zcu208 should open up with that board selected.  If it doesn't, double check the installation of rfsoc Explorer and look for any warnings or errors when you run the extra install m file script.

Also, it might be helpful to know which version of rfsoc Explorer you have installed.  There hasn't been any change to the plugin code and very little to the extra zip file since it's inception, and nothing that would cause this behaviou directly.

Mathworks does change their other support packages now and then, those packages do play a role for the zcu208.  However, others and myself have tried the latest versions; R2023b just about a month ago and it was all working.

Pls update with any status or info, thanks.

Thank you for your response, I greatly appreciate it! 

Just to recap:

I went to the first 10 steps and everything seemed to go great.  I ran the .m file entitled "installhdl208" and everything seemed to run fine.  I then also changed the "interfaces" file to a static IP address so that I can directly connect to the RFSoC board with an ethernet cable.  With this, I am able to ping the board, and everything works great.  With the premade bitstream I am able to run the first example (which generates and changes a tone frequency at 10 MHz intervals using the DAC and captures that data using the ADC).  Again, that ran with the premade bitstream.

When I tried to rebuild the ADC Capture demo above using the Workflow Advisor I am not able to target the ZCU208 board for IP Core Generation, only the ZCU111 or ZCU216 in this family.

The versions of each add-on/support package I have are:

MATLAB and Simulink R2023b

Avnet RFSoC Explorer 2.3.1

HDL Coder 23.2

HDL Coder Support for Xilinx FPGA Boards 23.2.0

HDL Coder Support for Xilinx RFSoC Devices 23.2.0

HDL Coder Support for Xilinx Zynq Platform 23.2.0

I am not able to get the ZCU208 board as a target platform when using the Workflow Advisor.

Something else that I should mention is that when I go to the Mathworks website for hardware support using HDL coder (below), the Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit is NOT listed under IP Core Generation Hardware:

HDL Language Support and Supported Third-Party Tools and Hardware - MATLAB & Simulink (mathworks.com)

Any and all help would be greatly appreciated, as I am not able to build any of the other examples because I cannot target the RFSoC ZCU208 in the Workflow Advisor.

Thank you for your help!

Thank you for your response, I greatly appreciate it! 

Just to recap:

I went to the first 10 steps and everything seemed to go great.  I ran the .m file entitled "installhdl208" and everything seemed to run fine.  I then also changed the "interfaces" file to a static IP address so that I can directly connect to the RFSoC board with an ethernet cable.  With this, I am able to ping the board, and everything works great.  With the premade bitstream I am able to run the first example (which generates and changes a tone frequency at 10 MHz intervals using the DAC and captures that data using the ADC).  Again, that ran with the premade bitstream.

When I tried to rebuild the ADC Capture demo above using the Workflow Advisor I am not able to target the ZCU208 board for IP Core Generation, only the ZCU111 or ZCU216 in this family.

The versions of each add-on/support package I have are:

MATLAB and Simulink R2023b

Avnet RFSoC Explorer 2.3.1

HDL Coder 23.2

HDL Coder Support for Xilinx FPGA Boards 23.2.0

HDL Coder Support for Xilinx RFSoC Devices 23.2.0

HDL Coder Support for Xilinx Zynq Platform 23.2.0

I am not able to get the ZCU208 board as a target platform when using the Workflow Advisor.

Something else that I should mention is that when I go to the Mathworks website for hardware support using HDL coder (below), the Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit is NOT listed under IP Core Generation Hardware:

HDL Language Support and Supported Third-Party Tools and Hardware - MATLAB & Simulink (mathworks.com)

Any and all help would be greatly appreciated, as I am not able to build any of the other examples because I cannot target the RFSoC ZCU208 in the Workflow Advisor.

Thank you for your help!

Hi,  Thanks for the info, I have a theory now why it is not working for you.  By the way, MathWorks does not directly support the ZCU208 board, that is correct.  However MathWorks does authorize Avnet to provide the ZCU208 support.  And so, Avnet provides the plugin code, examples for the ZCU208 and distributes it through the RFSoC Explorer add-on.

I suspect the issue may be because 2.3.1 RFSoC Explorer is not compatible with R2023b (it works and installs properly only with R2022a/b).  This makes me think you didn't really run through the parts of the instructions about installing RFSoC Explorer and it's unique FPGA bitstream first.  No problem with not doing that, it's just that it should have given you some warnings about not being compatible with R2023a/b.  Also know that RFSoC Explorer because of the limited privileges that MathWorks gives add-ons; it has to not only be installed but also run/opened at least one time.  Running it executes code that adds itself to the path, installing it without running it will not complete the setup of it and the hdl coder for zcu208 code.

The installhdl208.m script does attempt to check for RFSoC Explorer and outputs a warning if not found.  Not sure why exactly you aren't seeing a warning.  Here's a bit of the code from install208.m:

    try
        newPath = fileparts(which('Avnet_RFSoC_Explorer'));
        if ~isempty(newPath)
            newPath = fullfile(newPath, 'avnet_hdlcoder/zcu208');
            addpath(newPath);
            savepath;
        else
            disp('Warning: Avnet RFSoC Explorer path is empty or not installed, installation is incomplete.');
        end
    catch
        disp('Error: Avnet RFSoC Explorer is not installed, installation is incomplete.');
    end

Also, when I mentioned I tested this on R2023b I just realized I was not clear.  I did use it successfully but I had access to the next version of RFSoC Explorer which is supposed to be released any day now (there are some other brand new features coming in the next release that are not quite ready yet).  The next release will be compatible with R2023a/b.

So in the meantime, the easiest thing to do might be to use R2022a/b for a while until the next version of RFSoC Explorer is released?

Otherwise you can see in the install script above that it just needs to add the contents of the folder 'zcu208' found under the install location of RFSoC Explorer.  There isn't anything else needed from RFSoC Explorer to make HDL Coder for the ZCU208 work.  Matlab add-ons installation path depends on the OS and can also be customized, so your PC may be different than mine as far as what it's root path is.  After installing RFSoC Explorer add-on, you could try to search for the folder avnet_hdlcoder/zcu208 on your system and locate it that way, then try to addpath(..).  Do note that you must addpath then savepath, otherwise it will not be persistent.  After you do this, you can double check that Matlab has this new path in its master path setting.  If this doesn't just work for you, it will be a bit awkward to try to solve it in this forum and it is just a hack to try to get you moving forward.  Again, I think if you can, until the next verson of RFSoC Explorer comes out use R2022b?

Kind regards

Hi, I really, really appreciate your time to respond to me on this matter. 

I think that I sent you down a rabbit hole that did not need to be done.  I actually thought that I had successfully completed the install using the "installhdl208" script, but yesterday I saw that I WAS getting an error/warning that said 'Warning: Avnet RFSoC Explorer path is empty or not installed, installation is incomplete.'  To resolve this, I went to the Avnet RFSoC Explorer folder and then added that to my path.  After adding that to my startup path (which was a learning experience on its own), I was able to successfully run the "installhdl208" and the ZCU208 showed up as a target device!

I am sorry for the confusion and for second guessing why I was getting these errors, I should have looked at the warning more in depth.  I have not gone past actually setting the target device to the ZCU208 board, so I do not know if Avnet 2.3.1 will fully work with MATLAB R2023b, but I atleast see the device under Target Devices.

If I have any more questions I may write you soon, as me and my colleague are really diving into this now.

Thank you for your help!

I just thought of another question that may help and be beneficial to others who are doing this.  My version of Vivado is 2022.2, not the supported/MATLAB tested version 2022.1.  I see that there is the option to "Allow unsupported versions" and that allows me to get past that step in the Workflow Advisor.  I also get a warning that this may cause other issues and steps to not complete correctly.  I am wondering if you have any experience with this, and if I should just immediately downgrade to 2022.1 of Vivado, or if I should proceed with 2022.2 (and the "Allow unsupported versions" checked)?

Let me know what you think with this regard.  Again, I appreciate the help!

Thank you!

Glad you were able to get it working.

Regarding using a different version of Vivado, this is not feasible for the RFSoC development boards and these MathWorks tools.  One reason is that the tcl code for the hardware design that is generated is hard coded to only work with Vivado 2020.2 IP versions.  Another reason is that RFSoC HDL Coder is a platform that includes Linux device drivers for a specific Linux kernel version, a hardware design that is used to move data from the data converters to the PS (and then over the Ethernet port using libiio) and it also includes a v2020.2 PetaLinux OS image.  The way AMD/Xilinx made PetaLinux, it will not work with bitstreams created with a different version of Vivado.

Good luck with your project!