I am trying to generate HDL and SW project for ZCU208 IQ example.
I have matlab 2024b and 2025a installed.
Running though the HDL workflow advisor with unmodified slx, I get this error for both the Real and IQ examples. I get the error both in 2024b and 2025a.
I have the IIO stream blocks in my simulink library, but do not know what to do with them.
Note No driver block was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the software interface model.
Note No driver block was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the software interface model.
Note No driver block was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the software interface model.
Note No driver block was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the software interface model.
Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "MM2S_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "MM2S_Data" into a vector, and connect the vector port to the driver block.
Warning The AXI4-Stream IIO driver block cannot be automatically generated in the software interface model when a scalar port, "S2MM_Data", is mapped to AXI4-Stream interface "AXI4-Stream DMA". Before you generate code from the software interface model, add the AXI4-Stream IIO driver block from "Simulink Library Browser" -> "Embedded Coder Support Package for AMD SoC Devices" library, change "S2MM_Data" into a vector, and connect the vector port to the driver block.
Note No driver was generated for port(s) "Tile0 ADC Ch0 Data" mapped to interface "Tile0 ADC Ch0 Data" in the host interface script.
Note No driver was generated for port(s) "Tile0 ADC Ch0 Valid" mapped to interface "Tile0 ADC Ch0 Valid" in the host interface script.
Note No driver was generated for port(s) "Tile0 DAC Ch0 Data" mapped to interface "Tile0 DAC Ch0 Data" in the host interface script.
Note No driver was generated for port(s) "Tile0 DAC Ch0 Valid" mapped to interface "Tile0 DAC Ch0 Valid" in the host interface script.
Failed Generate Software Interface.
Generating new Zynq Software Interface model: gm_rfsocADCCapture_interface
SoC Blockset and SoC Blockset Support Package for AMD FPGA and SoC Devices are required to generate software interface model.
Zynq Software Interface model generation complete.
Generating new Xilinx Host Interface script: gs_rfsocADCCapture_interface.m
Xilinx Host Interface script generation complete.