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A question about the mapping relationships between the IO singal and its vaules

Former Member



In the Technical Reference Manual, I found "Configure MIO pin 46 for the RxD signal . Write 0x0000_12E1 to the slcr.MIO_PIN_46 register".

I just wanted to know why the 0x0000_12E1 corresponds to the RxD singal. I searched the characters "0x0000_12E1" in the TRM file, but no results returned. So there must not be any information about the mapping relationships between the IO singal and its vaules, such as the RxD singal correspondding to the "0x0000_12E1".

So where can I find the IO signal mapping relationshios?

  • 0

    Hi parallelcell,

    If you take a look in the latest version of the Technical Reference Manual V1.2, on page 1515 you will find the start of the register definition for the MIO_PIN_46 register.  This register is at address 0xF80007B8 and carries a reset value of 0x0000_1601.

    By setting the value of this register to 0x0000_12E1, the L3_SEL bits are changed from the default GPIO mode (000) to UART 0 RxD mode (111).

    Another way to understand the configuration of the MIO would be to experiment with the PS configuration within XPS.  Once the PS has been configured with the IO behavior you are targeting, you can export the configuration to SDK where you get a ps7_init.h and ps7_init.c file which contains the register configuration for the MIO.

    Take a look through these register definitions, they are useful in determining the IO signal mapping relationships.

    Regards,

    -Kevin

  • 0 in reply to zedhed

    I got it. Thanks for your reply vey much!

    I must read the technical reference manual carefully.

    Regards,
    parallelcell