AXI VDMA works, but the bottom few lines are not proper

Hi, all

I am trying to make a simple vdma test demo on zedboard.
Here is my steps.I want to send my own picture(32-bit per pixel) for FPGA processing.
1. I read my own picture to memory and copy them to DDR.
2. Using video dma core to send the input stream from DDR to my own pcore;
3. Samely, recieve the input stream from my pcore to DDR;
4. Finally, Write the output stream from DDR.
But i found the results in the bottom few lines are not proper, always comes with paceket loss?

Any ideas to fix this bug?

0 Former Member over 12 years ago

Did you flush the cache?
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0 Former Member over 12 years ago in reply to Former Member

Did you mean flush the vdma cache or OCM cache?
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0 Former Member over 12 years ago

From what I understood you use the MM2S Channel of the vdma, to the send an image from the ARM to the FPGA.
So the CPUs L1/L2 cache.
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0 Former Member over 12 years ago in reply to Former Member

Thanks for tips. Did you mean i must use fflush function in my programming begging? Now I increased the Vertical Size, such as 1000 to 1024, the results is OK.
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0 Former Member over 12 years ago

No, fflush() does something completely unrelated.
Are you on bare metal? Then try a Xil_DCacheDisable() in the beginning of your program.
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0 Former Member over 12 years ago in reply to Former Member

Oh, I am on Linux, not on bare metal. I found the Xil_DCacheDisable() in Zynq BSP, this function cannot use under linux. Any similar function to do this on Linux?
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0 Former Member over 12 years ago

How do you access the Memory? From Kernel or Userspace?
And if userspace, do you mmap or something else?
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0 Former Member over 12 years ago in reply to Former Member

Two methods I have done: insmod linux driver module or use mmap to operator registers.
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0 Former Member over 12 years ago

Details please, for mmap you could for example set pgprot_noncached() in the kernel.
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0 Former Member over 12 years ago in reply to Former Member

Oh, I use mmap such as: clear memory for DDR start address
void clearMemory(unsigned long startAddress, unsigned long size)
{
tint fd = open("/dev/mem", O_RDWR);
tunsigned long int i = 0;

tunsigned char *virtual_addr_in;

tvirtual_addr_in = (unsigned char *)mmap(NULL, size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, (off_t)startAddress);

tfor(i = 0; i < size; i++)
t{
ttvirtual_addr_in[i] = 0;
t}
tmunmap((void *)virtual_addr_in, size);
tclose(fd);
}
In the beginning of programming, i use this function to clear MM2S and S2MM Start Address.

And my application is under linux-digilent kernel(https://github.com/Digilent/linux-digilent).

In his xilinx_dma driver (https://github.com/Digilent/linux-digilent/blob/master/drivers/dma/xilinx_dma.c), it uses dma_pool, so I think this is a coherent dma mapping.
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