Hey everybody,
I'd like to use the SPI in the Zynq PS just to send some data to an external peripherial, but the SPI is not behaving as it is supposed to be.
The SPI instance is used as a master with manual chip select and manual start option, a CLK-prescaler of 4 and a reference clk of 200Mhz. No interrupts are used. Right now, SPI is routed to the MIO, SS[0] is omitted as discussed here (http://www.xilinx.com/support/answers/47511.htm), instead SS[1] is used for CS. Nothing else except the Uart is enabled in the design for testing purposes.
After the CS, the CS-signal goes down as it is supposed to be.
First unusual thing: The controller is enabled and data is written to the TX register. Then, the manual start bit is set to trigger the transfer. Now, the CLK-signal starts at a frequency of 33.3 Mhz (it is supposed to be at 200/4 = 50 MHz, acoording to the CLK-prescaler and the reference CLK). It does not change if I set another CLK-prescaler, only if I change the SPI reference clk frequency in the Zynq IP.
Second unusual thing: CLK and MOSI signal do not stop when the CS is deasserted, nor when the controller is disabled.
Third unusual thing: from the CS till the start of the CLK oscillation it takes about 500u00B5s, which in my opinion is far too long.
The control register has the right bits set, I tried using MIO and EMIO with the same results, I even build a project in PlanAhead to make sure that Vivado (I'm using 2013.2) is not the reason here.
Did anybody encounter this behaviour before? What is going wrong here? Is this a configuration problem or a problem of the hardware itself?
