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Former Member

Is there a way to implement the following design?

1) Run C code generated from Matlab in a real-time bare metal configuration on Arm core 0.

2) Run Android on Arm core 1 which will peek and poke data from the programmable logic and Arm core 0 and send it out to the PC via ethernet, or display it via a touchscreen.

3) Run custom or Matlab HDL Coder generated VHDL on the programmable logic.

The programmable logic and Arm core 0 are running real time application code and Android serves as a non real time interface between the host PC or visualization equipment.

I would like to get started on a design that implements this technology and am wondering if there is anybody out there willing to struggle through this with me.  Thanks for your time.

  ,Doctor K



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  • 0

    Good day,

    (first note that I've only been to XFest so take any info in this answer with a grain of salt as my understanding on EPP might be off).

    Would you care describing a bit more what kind of loads you are planning to implement in this design?

    I'm asking as it seems you want to have on one side (hard?) RT constraints with the bare metal programming side + HDL and on the other side the Android system.

    Having an OS (Android or anything alike) will probably kill your memory bandwidth as my understanding is that the DDR controller will be shared between both cores and the logic fabric (I suppose Android cannot work using only the internal cache and will have to access DDR regularly).

    So if your RT load is only a pipeline and does not require too much bandwidth from the DDR what you describe should be possible.

    I was also wondering why android? Xilinx will provide some linux images (and I hope also the ubuntu image that they were displaying in their demos at ESC). Linux is probably familiar for more people than Android. This might be a factor to have more interest in this project.

    Cheers
    DB

  • 0 in reply to Former Member

    The DDR controller on the processing system is separate from the Programmable Logic.  Multiple DDR chips could be added to the design and used in fabric in regard to the RT code portion to save bandwidth from the Android core.

    I would highly recommend reading this document:
    http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug873_zynq_ctt.pdf

    ... as well as the 7-series documentation on memory controllers.

    Android, if just streaming data via USB or Ethernet, should not be using DDR very often due to DMA.

    I concur that Linux probably the better option here for overhead reasons.

  • 0 in reply to Former Member

    Tim,
    thanks for your answer, I was thinking in my message about the ZED board not the general case, so please correct me if I'm wrong.

    Looking at your document (p14) there is a single DDR controller shared between all the blocks. So even if there are multiple controller ports (AXI?) with their own logic/queues, the global DDR BW is shared by all.

    After looking at the ZED schematic, the DDR is cut in 2 16bits packages with a shared address bus (p17) so I'm not sure to see how you can dedicate a package with its BW to the logic and the other one to the OS for example.

    http://zedboard.devcloud.acquia-sites.com/misc/files/ZedBoard_RevC.0_Schematic_120523_preliminary.pdf

    Also even if the transfers are mainly DMA, the fact the the OS might be handling video, Ethernet and potentially other activities will shrink the remaining BW for the rest...

    However I'm still convinced this platform has a great potential (I've ordered one).

    Cheers
    DB

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  • 0 in reply to Former Member

    Tim,
    thanks for your answer, I was thinking in my message about the ZED board not the general case, so please correct me if I'm wrong.

    Looking at your document (p14) there is a single DDR controller shared between all the blocks. So even if there are multiple controller ports (AXI?) with their own logic/queues, the global DDR BW is shared by all.

    After looking at the ZED schematic, the DDR is cut in 2 16bits packages with a shared address bus (p17) so I'm not sure to see how you can dedicate a package with its BW to the logic and the other one to the OS for example.

    http://zedboard.devcloud.acquia-sites.com/misc/files/ZedBoard_RevC.0_Schematic_120523_preliminary.pdf

    Also even if the transfers are mainly DMA, the fact the the OS might be handling video, Ethernet and potentially other activities will shrink the remaining BW for the rest...

    However I'm still convinced this platform has a great potential (I've ordered one).

    Cheers
    DB

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