let me introudce my project on Zedboard. I want to do the iteration scheme with vdma.
For example, In the 1st iteration, I copy the input stream data to the MM2S Start address1 (such as 0x1000000) which is connected to AXI HP0 port for vdma mm2s transferring. Then my pcore process the data and send the output stream to S2MM Start address1(0x12000000).
In the 2st iteration, I want to use the last iteration output instream as the input stream. So i reconfigure the vdma, configure the MM2S Start address1 as 0x12000000 and the S2MM Start address1 as 0x10000000. But this operation comes with error results.
Then i change the other method but need more time, i.e, Copy the last iteration output stream (0x12000000) to MM2S Start address 0x1000000, and reconfigure the vdma and my pcore, the result is OK, but it consumes more time.
So in the 2st iteration, Swap the S2MM and M2SS Start address for VDMA, is it correct?