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DMA prevents FreeRTOS lwip socket connections

Former Member

Hi!

I am using FreeRTOS and lwip to send data over a socket connection (running on cpu0).

When adding DMA transfer of data from the FPGA to cpu1 (running the standalone OS), the socket connection stops working.

FreeRTOS is running but there is no response to socket connection requests.
If DMA initialization is commmented out, then the socket connection works.

The DMA transfer works and was done based on the xaxidma_example_simple_poll.c example implementation.

Has anyone run into this, or have any idea how to solve it?

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  • 0

    It turned out that it is the interrupt used to trigger the DMA transfer that causes the problem.
    I am using the PL-PS interrupt port IRQ_F2P (P216), interrupt 61. The socket connection stopped working when using this interrupt.

    After modifying the function DistInit() called by XScuGic_CfgInitialize() in xscugic.c of the BSP, it now works.
    This is an automatically generated file, so it is not a very nice solution.
    Maybe there is a better solution?



    Here is the modified function:

    /*****************************************************************************/
    /**
    *
    * DistInit initializes the distributor of the GIC. The
    * initialization entails:
    *
    * - Write the trigger mode, priority and target CPU
    * - All interrupt sources are disabled
    * - Enable the distributor
    *
    * @paramtInstancePtr is a pointer to the XScuGic instance.
    * @paramtCpuID is the Cpu ID to be initialized.
    *
    * @returntNone
    *
    * @notettNone.
    *
    ******************************************************************************/
    static void DistInit_modified(XScuGic *InstancePtr, u32 CpuID)
    {
    tu32 Int_Id;

    #if USE_AMP==1
    t#warning "Building GIC for AMP"

    t/*
    t * The distrubutor should not be initialized by FreeRTOS in the case of
    t * AMP -- it is assumed that Linux is the master of this device in that
    t * case.
    t */
    treturn;
    #endif

    #if 0 // Removed, prevents socket connection from working
    tXScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET, 0UL);

    t/*
    t * Set the security domains in the int_security registers for
    t * non-secure interrupts
    t * All are secure, so leave at the default. Set to 1 for non-secure
    t * interrupts.
    t */

    t/*
    t * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
    t */

    t/*
    t * 1. The trigger mode in the int_config register
    t * Only write to the SPI interrupts, so start at 32
    t */

    tfor (Int_Id = 32; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=16) {
    tt/*
    tt * Each INT_ID uses two bits, or 16 INT_ID per register
    tt * Set them all to be level sensitive, active HIGH.
    tt */
    ttXScuGic_DistWriteReg(InstancePtr,
    tttttXSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
    ttttt0UL);
    t}


    #define DEFAULT_PRIORITY    0xa0a0a0a0UL
    tfor (Int_Id = 0; Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS; Int_Id+=4) {
    tt/*
    tt * 2. The priority using int the priority_level register
    tt * The priority_level and spi_target registers use one byte per
    tt * INT_ID.
    tt * Write a default value that can be changed elsewhere.
    tt */
    ttXScuGic_DistWriteReg(InstancePtr,
    tttttXSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
    tttttDEFAULT_PRIORITY);
    t}
    #endif

    #if 0 // Replaced, prevents socket connection from working
    tfor (Int_Id = 32; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=4) {
    #else
    tt// We are using interrupt 61, write only that.
    ttInt_Id = 60;
    #endif
    tt/*
    tt * 3. The CPU interface in the spi_target register
    tt * Only write to the SPI interrupts, so start at 32
    tt */
    ttCpuID |= CpuID << 8;
    ttCpuID |= CpuID << 16;

    ttXScuGic_DistWriteReg(InstancePtr,
    tttt     XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
    tttt     CpuID);
    #if 0
    t}
    #endif

    #if 0 // Removed, prevents socket connection from working
    tfor (Int_Id = 0; Int_Id<XSCUGIC_MAX_NUM_INTR_INPUTS;Int_Id+=32) {
    tt/*
    tt * 4. Enable the SPI using the enable_set register. Leave all
    tt * disabled for now.
    tt */
    ttXScuGic_DistWriteReg(InstancePtr,
    ttXSCUGIC_ENABLE_DISABLE_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET, Int_Id),
    ttt0xFFFFFFFFUL);

    t}

    tXScuGic_DistWriteReg(InstancePtr, XSCUGIC_DIST_EN_OFFSET,
    ttttttXSCUGIC_EN_INT_MASK);
    #endif
    }

  • 0 in reply to Former Member

    Apparently prvGetInterruptControllerInstance() should be used instead of XScuGic_CfgInitialize() as the interrupt controller already is initialized by FreeRTOS, but that is not possible as FreeRTOS is running on the other CPU?

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