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Software Application Development Issue with AXI DMA
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Related

Issue with AXI DMA

Former Member
Former Member over 10 years ago

Hello everyone,

I am using AXI DMA (v7.1) IP in my design with vivado 2014.4. I am trying to transfer data from FPGA to DDR and I have my custom IP in the design which generates and sends stream data to DMA with 4 bytes in a data beat and DMA sends it on to MM DDR. I am using the DMA in simple DMA mode with only write channel enabled. I have a couple of problems.

(1) The s_axis_s2mm_tready of the DMA is going to zero after four beats of data and is not reasserting.

(2) The documentation on DMA IP says and I quote "In the absence of any setup (that is, before it is programmed to run), AXI DMA will pull the s_axis_s2mm_tready signal Low after taking in four beats of streaming data. This will throttle the input data stream. To have a minimum amount of throttling, ensure that the AXI DMA is set up to run much before the actual data arrives".

Well I am setting up my DMA operations using the following tcl script which is quite straight forward.
 
mwr 0x40400030 0                                 
mwr 0x40400030 1             #Starting DMA operation
mwr 0x40400048 0x1ff00000    #destination address
mwr 0x43c00000 0xe           #command to start my IP
mwr 0x40400058 1024          #Number of bytes to be written

I am tightly following the programming sequence given in the documentation for the IP. Please somebody suggest me a reason for this.

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  • karthi14121998
    0 karthi14121998 over 3 years ago

    i am also facing same issue but what is solution!!!

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