hi everyone!
I created embedded project in Planahead by XPS.
After that i received user_logic file and modify it to
my design. but my design consists hierarchy, I mean i have to do "port map". Therefor i added my other vhd files to user_files' directory and update pao and prj files.
But when i syntesize and do P&R to it i have an error.It says that it not recognize the other vhd files and they are "blake boxes".
I don't know what to do can you help me?
thanks
daniel
