On Vivado 15.1 - I am trying to get the AXI VDMA interrupts to work. Both write and read interrupts are connected to the PS. Design has only Xilinx IP, no custom code. Once, upon programming the FPGA, I get one of the interrupts to occur, but only once (as seen on the ILA waveform). In the interrupt routine I clear the AXI VDMA status register but the interrupt does not occur again. Is there a working example interrupting the processor once a frame on both reads and writes. Looking for a Zynq (not micro blaze example)
