Add DDR data into Vivado model - zedboard

I initially had a doubt on how to read .txt matrices from an SD card to the Zedboard DDR memories: http://zedboard.org/content/read-txt-matrices-sd-ddr-zedboard

Well, I'm now able to read the five 1Mbyte maps into memory but I'm still having doubts on how to proceed.

So, what I have is an IP block from Vivado HLS that needs to receive those maps from the DDR memories, normalize them and then aggregate them all.

My problem is on the timeline of this process. Whithin SDK I load the matrices into DDR. Then to pass them to the IP block do I need an AXI DMA block added on Vivado? And if so, do I simply need to give the AXI DMA block the proper address of the DDR to initiate the tranfer?

And also, if I want to pipeline or do other loop directives how am I going to do that, i.e. in Vivado or in SDK?

I read a lot of tutorials and forums but I'm still confused (if not more) on how to tackle this.

Please give me some guidelines.

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0 drozwood90 over 9 years ago

Hi there,

I'm going to try to do my best to answer your questions:
**do I need an AXI DMA block added on Vivado?
-this depends on how fast you want to push the data. You can go as low complexity / slow as the AXI_GPIO, or as fast as the full blown DMA engine. In the Zynq Harrdware Speedway Lab6, we saw a more than 2x improvement in speed.

**And if so, do I simply need to give the AXI DMA block the proper address of the DDR to initiate the tranfer?
-There is a configuration that you will need to setup.
Adam Taylor gives a reasonable overview here:
http://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-Eight-Zynq-DMA-Adam-Taylor-s-MicroZed/ba-p/441092
and here:
http://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-DMA-Part-Two-Adam-Taylor-s-MicroZed-Chronicles-Part-29/ba-p/443324

**And also, if I want to pipeline or do other loop directives how am I going to do that, i.e. in Vivado or in SDK?
-Depends. If you are doing these optimization actions in your HLS block, you need to do it there. If you are doing it in teh HLD code area, you do it in the HDL code itself.

I hope this cleared things up for you. If not, please answer back so I can further assist you!

--Dan
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0 drozwood90 over 9 years ago

Hi there,

I'm going to try to do my best to answer your questions:
**do I need an AXI DMA block added on Vivado?
-this depends on how fast you want to push the data. You can go as low complexity / slow as the AXI_GPIO, or as fast as the full blown DMA engine. In the Zynq Harrdware Speedway Lab6, we saw a more than 2x improvement in speed.

**And if so, do I simply need to give the AXI DMA block the proper address of the DDR to initiate the tranfer?
-There is a configuration that you will need to setup.
Adam Taylor gives a reasonable overview here:
http://forums.xilinx.com/t5/Xcell-Daily-Blog/The-Zynq-PS-PL-Part-Eight-Zynq-DMA-Adam-Taylor-s-MicroZed/ba-p/441092
and here:
http://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-DMA-Part-Two-Adam-Taylor-s-MicroZed-Chronicles-Part-29/ba-p/443324

**And also, if I want to pipeline or do other loop directives how am I going to do that, i.e. in Vivado or in SDK?
-Depends. If you are doing these optimization actions in your HLS block, you need to do it there. If you are doing it in teh HLD code area, you do it in the HDL code itself.

I hope this cleared things up for you. If not, please answer back so I can further assist you!

--Dan
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