Hi guys,
got a quick question.. someone whos done this before can prolly help me.
in XPS i created a custom prepherial with a slave AXI port. the prepherial includes a BRAM with 2 memory regions).
after downloading everything and running my code, i can manage to read and write to one memory region (single bram) but i cant access the second bram?? i can write to it but i cant read!
Any suggestions?
when looking at the verilog file in the user_logic.v im thinking its something to do with the AXI_CS port.. but i cant manage to fix this.. any suggestions?