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VDMA SOFEarlyErr about Xilinx ZYNQ Base TRD test on Zedboard

Former Member

Hello everybody!

I just want to build a project which is similar to Xilinx Zynq Base TRD on my Zedboard. I have used one VDMA to write and read the video data to/ form the memory and the video patterns can be showed on the monitoru3002      Then, i add the second VDMA which is specially used by the Sobel Fitler IP to video data in/out u3002

I just want to use the first VDMA (S2MM channel)to write video data to  memory, and then use the seconde VDMA(MM2S) to read data from frame buffersu3002 But the second VDMA (MM2S channel ) gives the error status posted as follows:

INOUT VDMA WRITE Channel Status:    (first VDMA S2MM channel is ok)
         PARKPTR        = 0x00000000
        ------------------
         S2MM_DMACR       = 0x00010043
         S2MM_DMASR       = 0x00010000
         S2MM_STRD_FRMDLY = 0x00002000
         S2MM_START_ADDR0 = 0x30000000
         S2MM_START_ADDR1 = 0x30870000
         S2MM_START_ADDR2 = 0x310E0000
         S2MM_HSIZE       = 0x00001E00
         S2MM_VSIZE       = 0x00000438
         ----------------
         S2MM_HSIZE_STATUS= 0x00000000
         S2MM_VSIZE_STATUS= 0x00000000
         ----------------

FILTER VDMA READ Channel Status:  (Second VDMA in error status)
         PARKPTR          = 0x00000000
        ------------------
         MM2S_DMACR       = 0x00010003
         MM2S_DMASR       = 0x00015090      // SOFEarlyErr

         MM2S_STRD_FRMDLY = 0x00002000
         MM2S_START_ADDR0 = 0x30000000
         MM2S_START_ADDR1 = 0x30870000
         MM2S_START_ADDR2 = 0x310E0000
         MM2S_HSIZE       = 0x00001E00
         MM2S_VSIZE       = 0x00000438
         ----------------


How can i sovle this problem, please!u3000u3000

Any suggestion would be appreciate!

Dec

  • 0

    I suspect it may be caused by the frame sync signalu3002But i have set fsync signals almost the same as Xilinx Zynq Base TRD projectu3002The fsync signals in my project just like this:

    (1)First VDMA (INOUT_VDMA) :
    S2MM channel: 'SOF on TUSER0' as fsync input;(the fync output 's2mm_fsync_out' as the fsync input source for other IPs)
    MM2S channel:  mm2s_fsync = s2mm_fsync_out

    (2)Second VDMA(FILTER_VDMA)
    MM2S channel: mm2s_fsync = INOUT_VDMA::s2mm_fsync_out
    S2MM channel: s2mm_fsync = INOUT_VDMA::s2mm_fsync_out

    (3)An IP(AXI_HDMI_TX_16B) do the same job as logicvc (axis vid out + timing)
    fsync input = INOUT_VDMA::s2mm_fsync_out

    The datapath in my project is that:
    Video Source => INOUT_VDMA(S2MM) => FILTER_VDMA(MM2S) => SOBEL FILTER => FILTER_VDMA(S2MM) => AXI_HDMI_TX_16B => Monitor



            

  • 0

    @swordhe: did you ever get this to work?  I am trying to do almost the same thing (using the video scaler core instead of a sobel filter), but I think I'm having issues with the FSYNC signal across all of the VDMAs.  Any advice?