Regarding Cache and DMA

I have two questions regarding cache:

1. Should I invalidate the cache for the source/ destination memory on DDR for a DMA execution or the cache management unit does it?

2. If I disable the cache, can I use the L2 cache memory(512KB) as an on chip memory(Similar to SRAM)?

0 Former Member over 8 years ago

Hello Prathima,

This Xilinx Answer Record might help with question 1:
http://www.xilinx.com/support/answers/64839.html
If you still have questions regarding cache and DMA I would suggest posting the question on one of the Xilinx community forums:
http://www.xilinx.com/support.html#forums

The answer to question 2 is discussed in the post on the Xilinx community forums:
https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Can-the-L2-Cache-of-ZYNQ-be-able-to-used-as-RAM-just-like-the/td-p/297895

If you do want to try to 'lock' a segment of code in the L2 Cache and execute it these links might be useful:

http://www.wiki.xilinx.com/Zynq-7000+AP+SoC+Boot+-+Locking+and+Executing+out+of+L2+Cache+Tech+Tip
http://silica.com/wps/wcm/connect/7bfb089d-bd53-431e-ba51-9fbf04fd81ab/SILICA_Xilinx_Zynq_MMU_caches_control_ver1.0.pdf?MOD=AJPERES

-Gary
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