Hello,
I try to configure the PL from PS. Therefor I use the xdevcfg_polled_example.c from the xdevcfg documentation (just clicking in the .mss file).
The problem is, that it always hangs when polling the done flag in line 280.
I have no ide why.
I have used the .bin file from Vivado output and one generated by promgen (they are slightly different), but both did not work.
When first configurating the FPGA with JTAG and then reconfigurating with the example program, it does not hang and the logic is configured the right way. But that actually is not what I'm tryin to achieve.
Interestingly I found out, that when letting the debugger run free in that loop for some time, a reset occurs (just as if a buffer overflow occurs).
Can somebody help?
Best regards,
Yaro
P.S. I use Vivado 2014.2
