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Accessing Audio Lineout of Zedboard out of Simulink

Former Member

Hey Guys!

I am trying to ouptput Audio data from the PL to the Lineout or Headphone out of the I2S Audio Codec with MATLAB/Simulink and the corresponding Xilinx Support Packages.

I am using HDL Workflow Advisor to generate the bitstream for the PL.
In Point 1.2 "Set Target Interface" I have to set the "Target Platform Interface" for my audio Output.
I assume I must use "External Port" here. But what "Bit Range / Address / FPGA Pin" should I use?
I am very new to this topic, so I just found out something about Y8 pin for Signal AC-GPIO0 but I don't know what to do with this information. The "Bit Range / Address / FPGA Pin" must have the format {'LSB',...,'MSB'}.
Or am I totally on a wrong path?

Thansk for your answers!

Horst

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    Out of the box, the Zynq Hardware Support Packages do not support the codec interface, but there are a couple of things you can do to get things going. First, you'll need the right IP to interface the codec to the PL. We've used the information found at http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_Audio to be helpful. Once you have that, there are a couple of options:

    1. In R2015a, a new feature was introduced that allows you to import a custom reference design (specified in Vivado) into the HDL Workflow Advisor flow. Use this reference design feature, where the codec is part of your block diagram in Vivado (you can create this by using IP Packaging feature) and then use the IP Core Generation workflow to generate HDL IP which can be added to your reference design in Vivado. Make sure the correct audio pins are part of xdc file.

    2. If you don't have R2015a, black-box the codec code inside an atomic subsystem, and then:
         a.tIn Workflow Advisor step 1.2 declare all the codec pins as external port and assign the pin number on the board.  (as you pointed AC_GPIO0 is assigned pin u2018Y8u2019 on Zedboard.  Make sure you put the single quotes)
         b.tIn Workflow Advisor step 3.2 (or 4.1 if using Generic ASIC/FPGA workflow) add the codec files.  (once again make sure you have blackboxed your codec block in your Simulink model)

    Note, too, that MathWorks has a Zynq Progamming with MATLAB and Simulink training class available. See http://www.mathworks.com/zynq-training for more information.

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    Out of the box, the Zynq Hardware Support Packages do not support the codec interface, but there are a couple of things you can do to get things going. First, you'll need the right IP to interface the codec to the PL. We've used the information found at http://hamsterworks.co.nz/mediawiki/index.php/Zedboard_Audio to be helpful. Once you have that, there are a couple of options:

    1. In R2015a, a new feature was introduced that allows you to import a custom reference design (specified in Vivado) into the HDL Workflow Advisor flow. Use this reference design feature, where the codec is part of your block diagram in Vivado (you can create this by using IP Packaging feature) and then use the IP Core Generation workflow to generate HDL IP which can be added to your reference design in Vivado. Make sure the correct audio pins are part of xdc file.

    2. If you don't have R2015a, black-box the codec code inside an atomic subsystem, and then:
         a.tIn Workflow Advisor step 1.2 declare all the codec pins as external port and assign the pin number on the board.  (as you pointed AC_GPIO0 is assigned pin u2018Y8u2019 on Zedboard.  Make sure you put the single quotes)
         b.tIn Workflow Advisor step 3.2 (or 4.1 if using Generic ASIC/FPGA workflow) add the codec files.  (once again make sure you have blackboxed your codec block in your Simulink model)

    Note, too, that MathWorks has a Zynq Progamming with MATLAB and Simulink training class available. See http://www.mathworks.com/zynq-training for more information.

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