people...
I am an old school guy...
have designed fpga's by creating actual digital schemo in orcad using the XUNIFIED libraries, compiling to vhdl, importing to what use to be ISE and then creating the edf (or whatever file) to burn into the fpga for functionality....
always worked...timing great...
now..
using ZYNQ parts...
I have been able to build hardware in Vivado, and download into ZYNQ to use GPIO (i.e. AXI gpio..linked to PS..which I can read PL inputs and send out PL outputs via the PS...
what I need to do:
configure PL inputs that are clocked in by a external clock ...load them into a register bank and then send them out the Ethernet portion f the ZYNQ ( I can run the lwip no prob...good for an old doosch)..
the axi-gpio blocks seem to be tied to actual PL io...I need to put something in between the IO and get it into the PS for sending out the ethernet...
this is a radar app...I have 16 bits of data that is clocked in via an A/D converter (i.e. this clock is the main clock..everything syncs off this clock because the raw radar data is based on this clock)
any examples?...code?...even 1 bit data would be fine...
im old...I need some example....
again...16 bits coming in on hardware ports that need to me messaged and then read in to chunk out on ethernet..
any body..?...beuller?....anybody?...
beuller?
please help
grandpa out.
