I am trying to understand this example design with Cache coherent CDMA transfers from block RAM to OCM using the ACP port. http://www.xilinx.com/support/answers/50826.htm
1. How do you set this Xil_SetTlbAttributes(0xFFF00000,0x10C06) parameters? It seems to reflect the table in the page 74 of the Zynq-7000 All Programmable SoC Technical Reference Manual, but is it for the level 1 or level 2 page table?
2. Caching doesnu2019t seem be enabled explicitly and so how does a writeback policy get activated to make the l1 or l2 coherent?
3. Is there way to measure caches hits, if I make the design the otherway around. CDMA will make the data transfers from OCM to the BRAM after initialization of the values so there the transfer latency should be of one cache hit. Is there way to verify this operation.
Thanks in Advance.