Ethernet does not work with Linux 3.14

Hi,

I have created a new rootfs with buildroot. Kernel is home-made from linux-xlnx (derived itself from vanilla 3.14). I also use device tree from linux-xlnx (zynq-zed.dtb).

On startup, XEMAC IP is detected, and configured :

[    0.471999] libphy: XEMACPS mii bus: probed
[    0.477048] xemacps e000b000.ps7-ethernet: invalid address, use assigned
[    0.483739] xemacps e000b000.ps7-ethernet: MAC updated 02:c5:60:0f:58:af
[    0.490579] xemacps e000b000.ps7-ethernet: pdev->id -1, baseaddr 0xe000b000, irq 54
[...]
[    6.111054] xemacps e000b000.ps7-ethernet: Set clk to 115151514 Hz
[    6.117443] xemacps e000b000.ps7-ethernet: link up (1000/FULL)

ifconfig shows it configured.

But, when i ping zedboard, which IP address is 192.168.254.127, from my PC (192.168.254.4), ping says "host unreachable".
tcpdump on zedboard shows that it receives an ARP request and send an ARP reply. But on PC, reply is never received.

ifconfig on zedboard show that TX packets counter is incremented, with no error/dropped packet.

So, it seems zedboard does not send packets on eth0 (or it sends messy bits).
Hardware is not broken as ping works when i boot zedboard on SDcard from zedboard box.

I think about a misconfiguration but i don't know how to look for.

Anyone has an idea ?

0 Former Member over 11 years ago

After digging more, I've found that : http://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/zc706-ethernet-does-not-work/m-p/517169/highlight/true#M9881

[ 6.111054] xemacps e000b000.ps7-ethernet: Set clk to 115151514 Hz

Clock should be set to 125MHz for a gigabit link. How can I modify this clock ?
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0 Former Member over 11 years ago

You can check/change the clock to the Ethernet 0 by Opening your Block Design in Vivado and double clicking on the Zynq Processing System Block. Then select 'Clock Configuration' and expand IO Peripheral Clocks.

Where did you get this hardware design? This clock should have been set correctly when using the board presets.

-Gary
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0 Former Member over 11 years ago in reply to Former Member

My design is a new project created from zedboard presets with Vivado 2014.2.

In vivado, clock for ENET0 is set to 124MHz for a speed of 1G. I will try another generation after toggling this value.

Yesterday, i forced eth0 to 100M with ethtool, ans it works (clk is set to 24 MHz). But renegociating it to 1G, and clock is set to an incorrect value.
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0 Former Member over 11 years ago in reply to Former Member

After regenerating HW design and rebuilding U-boot with new ps7_init files, eth0 is still misconfigured (ethernet driver says that clock is set to 113 MHz).

For now, I fall back to 100M to keep on working on this board.

Sylvain
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0 Former Member over 10 years ago

I had the exactly same problem with microZed. (Vivado 2014.2)
I had the board preset from Zedboard.org.

After creating the hardwer design I checked the Clock/Configuration/Advanced Clocking menu in Vivado and I noticed that the PLL Multipliers are not the same values as in Vivado 2014.1 with built in microZed board preset.
I have enabled the Override Clocks feature and I have changed the IOPLL Multiplier and ofcourse the First and Secound Divisor values also related to the IOPLL.

Now its working for me perfectly.
(xemacps : ... set clk to 124.9 MHz.) Ping is working also.

Clock parameters for me are now the followings:

PLL Divisor: IOPLL
Multiplier: 30
PLL Freq(MHz) 1000

First Divisor (ENET0) : 8
Secound Disor (ENET0) : 1

Peto
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0 Former Member over 10 years ago in reply to Former Member

Just to clarify, you used the MicroZed Board Definition Install for Vivado 2014.2 download from the MicroZed documents page?

If so, did you install into the Vivado installation or into a User Repository?

-Gary
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0 Former Member over 10 years ago

Yes I have used the board definition files that you linked in.
And Yes I used the User Repository intall option.
I deleted the original board definition files from Vivado folder (2014.2/data/boards)

I am using Ubuntu 14.04. The intresting thing is that I also tried it out today under Windows 8.1 and the clock multiplier values are set to the correct values there.

Under Ubuntu when I create a new project, set microzed 7010 rev f board, add zynq ip, run block automation my clcok parameters are the following:

Input frequency (MHz) : 33.333333

PLL Divisor: IOPLL
Multiplier: 34
PLL Freq(MHz) 1122

First Divisor (ENET0) : 9
Secound Disor (ENET0) : 1

Peto
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0 Former Member over 10 years ago

I'm having the same problem here, using Vivado 2014.2 under Lubuntu 32 bit and using the MicroZed Board Definition Install for Vivado 2014.2 (installed in the Vivado directory).

Under "Advanced Clocking" the default values are:
Input Frequency: 33.333333, CPU Clock Ratio 6:2:1
ARMPLL: Multiplier: 40, PLL Freq (MHz): 1320
DDRPLL: Multiplier: 32, PLL Freq (MHz): 1056
IOPLL: Multiplier: 34, PLL Freq: 1122

ENET0: IO PLL, First Div. 9, Sec. Div 1, Act. Freq 124

Obviously, there is something wrong, as the resulting PLL frequencies are computed wrong: 33.333333Mhz*34 is 1133Mhz, not 1122.

Interestingly, under Win 7 64 Bit, Vivado 2014.2 with the same MicroZed Borad definition install shows the correct values (PLL Freqs 1333.33/1066.67/1000.00).

Under Lubuntu, Vivado seems to use an Input Frequency of 33Mhz instead of the 33.333333Mhz it displays.

What is wrong here?

dikon
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0 Former Member over 10 years ago

There is a similar issue reported on the Xilinx Community Users Forum that was corrected by setting the OS regional settings to US:

http://forums.xilinx.com/t5/Embedded-Development-Tools/Cannot-Set-specific-clock-frequency-for-PL-Fabric-Clocks-in/td-p/528867/page/2

You might give that a try.

-Gary
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0 Former Member over 10 years ago in reply to Former Member

That's it, thanks very much!

After changing the locale LC_NUMERIC from de_DE.UTF-8 to en_US.UTF-8 it worked.
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