I have added one axi epc ip core in my project which will be driving some signals of my external user glue logic. I am operating the axi epc in asynchronous mode. I tried to search for design examples/reference designs for this particular IP but I didn't found any on the Xilinx Website/Forums. If anyone can help me with where I can find it or with the source codes for testing when I export the the h/w to sdk.
Thanks.