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HDL sample time in Simulink for MiniZed

100stefanoo

Hi all

I'm developing an acquisition and elaboration system using Simulink for the MiniZed.

Specifically acquisition from I2C peripheral (PMOD) and fixed point operations.

My problem:

using an oscilloscope i measured that each step of execution on the board occur every 1.3 microseconds.

I would like to increase this value (which is called "model sample time") but I can only achieve this for the simulation, not for when the code is running on the board.

I've opened a question also on the matlab forum:

https://www.mathworks.com/matlabcentral/answers/414117-how-to-set-stateflow-transition-time-for-hdl-generation

To that I would like to add that the issue is not just related to Stateflow transitions and physical ports.

I measured the same value using a simple counter block connected to an axi4-lite port.

What is the way to set the model sample time so that is compatible with HDL code generation?

  • 0

    The "execution" time in generated HDL code is dictated by the clock being used in the programmable logic (PL)..  The HDL timing is 100% deterministic and repeatable. However It is completely decoupled from Simulink simulation time.

    To model it in Simulink, I imagine you would need to create enabled subsystems that are enabled at your HDL clock frequency. MathWorks may have a more elegant/built-in method.

    /Matt

  • 0 in reply to mbrown

    Thanks Matt that's exactly how I was thinking about the thing.

    For slow operations (miliseconds order) I managed to have a working implementation setting the Processor/FPGA synchronization to "Coprocessing - blocking", in this case the Simulink interface step is used.

    For the Stateflow transitions to drive physical ports (microseconds order) this workaround doesn't even get close.

    As you stated a more elegant (hopefully built-in) method would be welcome.

    Thanks again!

  • 0

    guess I figured how to make the clock and the system get along.

    In the Workflow Advisor section 3.1.2 - Advanced Options the clock setting "Oversampling factor" could be set (from the default 64) to 1 and measure my SCL reach 50MHz.
    Then setting this factor to 500 my SCL runs at 100KHz.
     
    They call it Oversampling factor but it does quite the opposite... anyways... 
     
    Could you help me to unravel this last mistery: what clock is this referring to? sometimes I found references to a 50MHz clock some other times to a 100MHz clock.
     
  • 0

    We use an MMCM in the Zynq PL to divide a 100MHz clock down to 50MHz.

    The 50MHz clock is used for all logic created by HDL Coder.