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Driving differential SPI to JC Pmod connector

Former Member

Hello guys,

I have been working on SPI 1 on the PS section of the zedboard to drive one of my spi slave board. I have routed the MOSI, MISO , SCLK and CS pins to JE PMOD connector and this was working fine.

But now I need to use differential SPI, so these SPI pins are driven through EMIO  to the differential PMOD connector JC.The connections in the vivado are done in the following way:

SPI1_SCLK_O is connected to the input of OBUFDS, and the _P and _N outputs of OBUFDS are made external so that I can allocate appropriate pins to them.

Similarly, SPI1_MOSI_O and SPI_SS_O are connected to OBUFDS, and SPI1_MISO_I is connected to IBUFDS.

But when I try to do the pin mapping, it only allows me to map the _P differential pins of the differential buffer, it does not allow me to map _N pins.

I shall be generating this hardware in Vivado and exporting it to SDK. And SDK will have the C program to drive SPI.
 
Is this the correct way to drive the SPI in differential way ?
Do I need to make any other changes to this ?
Kindly suggest me on this.
Thanks a lot.
  • 0

    Hello,

    I would suggest adding a 'Utility Buffer' IP to your Vivado block diagram and configuring it to IBUFDS/OBUFDS/IOBUFDS to bridge between the 'single ended' EMIO signals and the external differential signals. You can set the pins and IO Standards in your constraints file.

    If you do use differential signals with the SP SPI controller you need to tie the SSIN signal high in your design.

    The real issue I see with using the ZedBoard JC or JD PMOD connectors in this fashion is that there are in IO Bank 13, which is fixed to 3.3V VCCIO. While you can receive some differential signals with the VCCIO different than the differential IO standard (like receiving LVDS_25 with VCCIO set to 3.3V as long as you do not use the internal differential termination) I don't think that you can drive a differential output with a different IO standard. I don't know of any 3.3V differential standard supported by the Zynq device. You will need to do your own research to confirm this. Here are a couple of places to start:

    http://www.xilinx.com/support/documentation/data_sheets/ds187-XC7Z010-XC7Z020-Data-Sheet.pdf

    http://www.xilinx.com/support/documentation/user_guides/ug471_7Series_SelectIO.pdf

    http://www.xilinx.com/support/answers/43989.html

    If your SPI Slave board supportes either 2.5V or 1.8V IO you could connect to it via the FMC connector, which supports both IO Bank 34 and IO Bank 35, which can be set to either 1.8, 2.5, or 3.3V VCCIO.

    -Gary

  • 0

    It was mentioned to me that there is an IO standard, TMDS33, that will work on a Zynq IO bank set to 3.3V. You may need to adjust your terminations (TMDS requires 3.3V pullups) and may need to level shift voltage levels based on the IO standard of your SPI slave card.

    I guess the larger question is, do you really need a differential SPI interface? What type of board are you interfacing to?

    -Gary

  • 0 in reply to Former Member

    Hi Gary,

    Thanks for informing me about this. I do really need differential spi to drive my slave. From the datasheet of my slave I understand that following voltage ranges are used while driving in differential mode:


    LVDS Input Common-Mode Voltage: Suggested common-mode level is 1.25 V.
    LVDS Output Common-Mode Voltage: 1.25V
    LVDS Input Differential Voltage: Suggested differential voltage is ±350 mV.
    LVDS Output Differential Voltage: ±350 mV.
     

    Currently, I am using 'Utility buffers' in my vivado design, and I have connected MOSI, SCLK and SS, each of them to 'OBUFDS' in order to generate differential signals like MOSI_P, MOSI_N etc for each of the signals. MISO is connected to the output of  'IBUFDS' which takes MISO_P and MISO_N as inputs.

    And I have generated constraints file for mapping this pins as follows:

    set_property PACKAGE_PIN AB7 [get_ports {MOSI_P[0]}]
    set_property PACKAGE_PIN AB6 [get_ports {MOSI_N[0]}]
    set_property PACKAGE_PIN Y4 [get_ports {SCLK_P[0]}]
    set_property PACKAGE_PIN AA4 [get_ports {SCLK_N[0]}]
    set_property PACKAGE_PIN R6 [get_ports {SS_P[0]}]
    set_property PACKAGE_PIN T6 [get_ports {SS_N[0]}]
    set_property PACKAGE_PIN U4 [get_ports {MISO_N[0]}]
    set_property PACKAGE_PIN T4 [get_ports {MISO_P[0]}]image
     
     
    I am bit confused about the appropriate voltage bank I need to select for running my slave in differential mode.
    It would be great if you have any suggestions on this and thanks a lot for all the help.
     
    Darpan
  • 0

    Hello Darpan,

    Those specs match LVDS_25. As discussed in the previous post above, while you can receive LVDS_25 on IO Banks with a 3.3 VCCIO, you cannot drive LVDS_25 signals on a bank with 3.3 VCCIO. The ZedBoard JC and JD PMODs are on Zynq Bank 13, which is fixed at 3.3 VCCIO. So, if you need to use LVDS_25, you will need to move your SPI connections to the FMC connector and set the ZedBoard VADJ to 2.5 V, or you will need to provide an interface circuit to level shift your outputs from the PMOD connectors to LVDS levels.

    -Gary