Hi.
I am facing issue with reading from DDR memory to PL(led's).
i have connected fabric hardware like shown in image on this link https://drive.google.com/folderview?id=0Byl0l4ua8ptEaXJ2SUFibVZJekk&usp=sharing , address allocated to all hardware are also shown in image.
also i have written following code for configuring hardware
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CODE :
/*
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A
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* ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
* FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY
* AND FITNESS FOR A PARTICULAR PURPOSE.
*
*/
/*
* helloworld.c: simple test application
*
* This application configures UART 16550 to baud rate 9600.
* PS7 UART (Zynq) is not initialized by this application, since
* bootrom/bsp configures it to baud rate 115200
*
* ------------------------------------------------
* | UART TYPE BAUD RATE |
* ------------------------------------------------
* uartns550 9600
* uartlite Configurable only in HW design
* ps7_uart 115200 (configured by bootrom/bsp)
*/
#include <stdio.h>
#include "platform.h"
#include "ps7_init.h"
#include <xil_io.h>
#include "xscugic.h"
#include "xparameters.h"
/********************************Write Data**********************************/
void StartDMATransfer (unsigned int dest_addr , unsigned int length)
{
tu32 addr1;
tu32 addr2;
taddr1 = XPAR_AXI_DMA_0_BASEADDR + 0x48;
taddr2 = XPAR_AXI_DMA_0_BASEADDR + 0x58;
t//Writing Address to S2MM_DA register
tXil_Out32(addr1 , dest_addr);
t//Writing Length to S2MM_LENGTH register
tXil_Out32(addr2 , length);
}
/********************************Read Data**********************************/
void Read_Data (unsigned int dest_addr , unsigned int length)
{
ttu32 addr1;
ttu32 addr2;
ttaddr1 = XPAR_AXI_DMA_1_BASEADDR + 0x18;
ttaddr2 = XPAR_AXI_DMA_1_BASEADDR + 0x28;
tt//Writing Address to MM2S_DA register
ttXil_Out32(addr1 , dest_addr);
tt//Writing Length to MM2S_LENGTH register
ttXil_Out32(addr2 , length);
}
/*******************Interrupt_Handler*******************/
XScuGic InterruptController0;
XScuGic InterruptController1;
static XScuGic_Config *GicConfig0;
static XScuGic_Config *GicConfig1;
u32 frame_count0;
u32 frame_count1;
/*************************Write Interrupt***********************/
void InterruptHandler1(void)
{
tu32 tmpval;
tu32 addr1;
taddr1 = XPAR_AXI_DMA_0_BASEADDR + 0x34;
t// xil_printf("Interrupt Acknowledgment.
r");
t// Interrupt clear and write to bit no. 12 of S2MM_DMASR
ttmpval = Xil_In32(addr1);
ttmpval = tmpval | 0x1000;
tXil_Out32(addr1,tmpval);
t//DRAM DATA PROCESSING
tframe_count1++;
tif(frame_count1 > 10000000)
t{
ttxil_printf("Frame Number write : %d
r",frame_count1);
ttreturn ;
t}
t//initiate DATA Transfer
t//StartDMATransfer(0xa000000+128*frame_count,256);
tStartDMATransfer( 0xa000000, 256);
}
int SetupInterruptSys1(XScuGic *XScuGicInstancePtr1)
{
tXil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler) XScuGic_InterruptHandler,XScuGicInstancePtr1);
tXil_ExceptionEnable();
treturn XST_SUCCESS;
}
int Initial_Interrupt1(deviceID1)
{
tint status;
tGicConfig1 = XScuGic_LookupConfig (deviceID1);
tif(NULL == GicConfig1 )
t{
ttreturn XST_FAILURE;
t}
tstatus = XScuGic_CfgInitialize (&InterruptController1,GicConfig1,GicConfig1->CpuBaseAddress);
tif(status != XST_SUCCESS)
t{
ttreturn XST_FAILURE;
t}
tstatus = SetupInterruptSys1( &InterruptController1 );
tif(status != XST_SUCCESS)
tt{
tttreturn XST_FAILURE;
tt}
tstatus = XScuGic_Connect (&InterruptController1,
tttXPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR,
ttt(Xil_ExceptionHandler)InterruptHandler1,
tttNULL);
tif(status != XST_SUCCESS)
ttt{
ttttreturn XST_FAILURE;
ttt}
tXScuGic_Enable (&InterruptController1 , XPAR_FABRIC_AXI_DMA_0_S2MM_INTROUT_INTR);
treturn XST_SUCCESS;
}
/*************************Read Interrupt************************/
void InterruptHandler0(void)
{
tu32 tmpval;
tu32 addr1;
ttaddr1 = XPAR_AXI_DMA_1_BASEADDR + 0x04;
t// xil_printf("Interrupt Acknowledgment.
r");
t// Interrupt clear and write to bit no. 12 of S2MM_DMASR
ttmpval = Xil_In32(addr1);
ttmpval = tmpval | 0x1000;
tXil_Out32(addr1,tmpval);
t//DRAM DATA PROCESSING
tframe_count0++;
tif(frame_count0 > 10000000)
t{
ttxil_printf("Frame Number Read: %d
r",frame_count0);
ttreturn ;
t}
t//initiate DATA Transfer
t//StartDMATransfer(0xa000000+128*frame_count,256);
tRead_Data(0xa00000c, 256);
}
int SetupInterruptSys0(XScuGic *XScuGicInstancePtr0)
{
tXil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,(Xil_ExceptionHandler) XScuGic_InterruptHandler,XScuGicInstancePtr0);
tXil_ExceptionEnable();
treturn XST_SUCCESS;
}
int Initial_Interrupt0(deviceID0)
{
tint status;
tGicConfig0 = XScuGic_LookupConfig (deviceID0);
tif(NULL == GicConfig0 )
t{
ttreturn XST_FAILURE;
t}
tstatus = XScuGic_CfgInitialize (&InterruptController0,GicConfig0,GicConfig0->CpuBaseAddress);
tif(status != XST_SUCCESS)
t{
ttreturn XST_FAILURE;
t}
tstatus = SetupInterruptSys0( &InterruptController0 );
tif(status != XST_SUCCESS)
tt{
tttreturn XST_FAILURE;
tt}
tstatus = XScuGic_Connect (&InterruptController0,
tttXPAR_FABRIC_AXI_DMA_1_MM2S_INTROUT_INTR,
ttt(Xil_ExceptionHandler)InterruptHandler0,
tttNULL);
tif(status != XST_SUCCESS)
ttt{
ttttreturn XST_FAILURE;
ttt}
tXScuGic_Enable (&InterruptController0 , XPAR_FABRIC_AXI_DMA_1_MM2S_INTROUT_INTR);
treturn XST_SUCCESS;
}
/********************************Initialize DMA**********************************/
int Initial_AXI_DMA(void)
{
ttunsigned int tmp0;
ttunsigned int tmp1;
ttu32 addr1;
ttu32 addr2;
ttaddr2 = XPAR_AXI_DMA_1_BASEADDR + 0x00;
ttaddr1 = XPAR_AXI_DMA_0_BASEADDR + 0x30;
tt// setting S2MM DMACR.RS = 1
tttmp0 = Xil_In32(addr1); // read from address 0x40400000 + 0x30
tttmp0 = tmp0 | 0x1001; // Modifying value // enable data unit & interrupt when done
ttXil_Out32(addr1,tmp0); // writing back to the same address 0x40400000 + 0x30
tttmp0 = Xil_In32(addr1);
ttxil_printf("DMA S2MM Control Register Value is %x
r",tmp0);
tt// setting MM2S DMACR.RS = 1
tttmp1 = Xil_In32(addr2); // read from address 0x40400000 + 0x30
tttmp1 = tmp1 | 0x1001; // Modifying value // enable data unit & interrupt when done
ttXil_Out32(addr2,tmp1); // writing back to the same address 0x40400000 + 0x30
tttmp1 = Xil_In32(addr2);
ttxil_printf("DMA MM2S Control Register Value is %x
r",tmp1);
ttreturn 0;
}
/*******************My_ip*******************************/
int Initial_My_IP(unsigned int size)
{
tXil_Out32(XPAR_AXI_GPIO_0_BASEADDR, size); // set Frame Size
tXil_Out32(XPAR_AXI_GPIO_1_BASEADDR, 1); // Enable to generate Samples
treturn 0;
}
/*****************************MAIN***************************/
int main()
{
init_platform();
ps7_post_config();
char c;
unsigned int d;
xil_printf("Initializing AXI_DMA
r"); // Initializing DMA
Initial_AXI_DMA();
xil_printf("Do You Want To Perform Write.....?
r");
xil_printf("y for Yes or n for No
r");
c= getchar();
if(c=='w')
{
txil_printf("Enabling My_ip to Generate Samples ............
r"); // Initializing My_IP
tInitial_My_IP(64); // End of frame after 128 Bytes (32 words) transferred
txil_printf("Enabling Write Interrupt Handler ...........
r"); // Initializing Interrupts
tInitial_Interrupt1(XPAR_PS7_SCUGIC_0_DEVICE_ID);
txil_printf("Writing Begins...........
r"); // Initial DMA Transfer
tStartDMATransfer( 0xa000000, 256);
tc = 'a';
}
else if(c=='r')
{
tXil_DCacheDisable();
txil_printf("Enabling read Interrupt Handler ...........
r"); // Initializing Interrupts
tInitial_Interrupt0(XPAR_PS7_SCUGIC_0_DEVICE_ID);
txil_printf("Reading Begins...........
r"); // Initial DMA Transfer
tRead_Data(0xa000004,256);
tc = 'a';
td = Xil_In32(0xa000004);
txil_printf("value = %d
r",d);
}
else
{
tc='a';
}
return 0;
}
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ISSUES :
1- Reading abrupt values but able to see the correct value.
2- Writing correct values but don't it is uncontrollable.
3- Need a proper explanation.
