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Standalone program for SDIO test failed

Former Member

I am trying to run a standalone sd card read & write program to test the speed as follow:



   // SDIO Controller Test
   static XSdPs ps7_sd_0;

   XSdPs_Config * SdConfig_0;

   u8 RxBuffer[512*2];
   int Status;

   SdConfig_0 = XSdPs_LookupConfig(XPAR_PS7_SD_0_DEVICE_ID);
tif (NULL == SdConfig_0) {
ttreturn XST_FAILURE;
t}

tStatus = XSdPs_CfgInitialize(&ps7_sd_0, SdConfig_0, SdConfig_0->BaseAddress);
tif (Status != XST_SUCCESS) {
ttprint("Sd Config failed !
r");
ttreturn XST_FAILURE;
t}


tStatus = XSdPs_SdCardInitialize(&ps7_sd_0);
tif (Status != XST_SUCCESS) {
ttprint("Sd0 Initialization failed !
r");
ttreturn XST_FAILURE;
t}

t// read and write test
tStatus = XSdPs_ReadPolled(&ps7_sd_0, 0x01, 0x01, RxBuffer);
tif (Status != XST_SUCCESS) {
ttprint("Sd1 Read failed !
r");
ttreturn XST_FAILURE;
t}


The last read function fails, anyone knows why ?


  • 0

    Hi doonny,

    Rather than read and write raw data to the SD card, won't you need some sort of file system at some point?

    The Zynq First Stage Boot Loader (FSBL) is a provided SDK application template which accesses a FAT32 file system on the SD card.  I would recommend starting with that code as an example of accessing the SD card.

    Regards,

    -Kevin

  • 0

    Hi kevin,

       Thanks,  I am not intend to access the files on the SD card actually. I only want to quickly test the highest frequency that the EMIO can support when configuring another sd controller through it.



       I have solved the problem. There is a diskio.c provided by xilinx which can be used for reference.  There is a lot issues with using a second sdio controller through EMIO, people are disscusing it on the xilinx forums.



       Fortunately, I have managed to fix the mmc drivers and succefully mount the second SD card under linux using 5MHz frequency.



       By the way, do you know anyway that can enhance a clock signal's drive capability in PL with zero delay ?  The EMIO really does a bad job when routing clock signals.




  • 0

    Hello Doonny,

     

    If your clock signal is within the frequency range of the Zynq PL Clock Management Tiles (CMT), 19 MHz to 800 MHz if using the PLL, you can use a CMT to implement a 'zero delay' clock buffer.

     

    -Gary