High Z behavior of SPIPS interface in idle state?

Hallo,
I am new in the world of Zynq and I am trying to work with the xspips driver as master. I donu2019t find a good documentation so I ask my question her. The digital design seems to work. The SPI signals are driven to the EMIO. I am also able to write bytes to the SPI. But it seems to be that the SPI driver switches all signals to high Z if the driver is in idle mode. This is a problem in special on the CS signal. I got these conclusion because when I measure the CS signal with an oscilloscope (Analog Discovery Zin~2MOhm) the CS signal got driven to GND slowly after the driver switched it to VCC.
Is it possible that the driver switches the Signals to HighZ? Is there a possibility to avoid this?
Youu2019re sincerely
Stephan

0 zedhed over 10 years ago

Hi Stephan,

Since it is an EMIO connection, you could try adding a constraint to your XDC file to enable the internal pullup resistor on the IO that corresponds to the CS signal.

Something like this:

set_property PACKAGE_PIN "Y11" [get_ports "EMIO_CS"]
set_property pullup "TRUE" [get_ports "EMIO_CS"]

You might also consider using the AXI Quad SPI controller instead. It is more flexible than the PS SPI controller if you have the space in your Programmable Logic section.

http://www.xilinx.com/support/answers/47511.html

http://zedboard.org/content/ps-spi-pmod-je7-hardware-system

Regards,

-Kevin
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0 Former Member over 10 years ago

Thank you, this was the solution.
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