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PL memory access from PS in Petaliunx

Former Member

Hi,
I have a custom designed peripheral in the PL of the Zynq that reads an external ADC and stores the results in a section of BRAM. I want to be able to access this from a Linux application to do further processing and transmission. The BRAM is connected to the AXI bus via an AXI BRAM Controller and the relevant parts are in the device tree for Linux. So this means I can access the memory from Linux and in my application.
The problem lies when I try to write the the memory, I only seem able to write to the first 32 bits. Using an ILA connected to the AXI port on the BRAM controller I only see activity when I write to the first address (0x43C00000), if I increment the pointer in Linux and try to write there is no bus activity. However the write is reflected in SDKs memory viewer when I look at the location of the pointer(the memory mapped location of the BRAM).
Is this lack of activity on the AXI bus expected or is it not actually writing?
When writing to the status register (stored in the BRAM) the peripheral never seems to react, this leads me to think the writes are never actually going through. But as far as I know there is no way to check this.
Can anyone offer any help?
Thanks

  • 0

    This sounds like a hardware issue with your custom peripheral. It might be easier to debug the hardware at a 'bare metal' level using SDK. Perhaps some simple C code run in debug mode in the SDK. Another thing to try might be to build a simple BRAM peripheral using just the AXI_BRAM controller and a block of BRAM and see if you can read and write correctly. If this works it would validate the expected behaviour of the AXI BRAM Controller.

     

    -Gary

  • 0

    Hi Gary,
    First of all thanks for your reply. I have since tracked it down to my bram controller. The problem seems to be that in synthesis a lot of the bram controllers logic is optimised out. I can't understand why this is happening, I suppose the synthesiser must be thinking it redundant. But pre and post synthesis behavioral show totally different operations of the controller. Mainly a few inputs are ignored and not connect to anything and lots of logic is gone.
    Any suggestions as to how I might stop this happening, or what the cause is?  

  • 0

    Make sure that you have provided a clock and a reset input to the BRAM controller as well as a connection to an AXI Master interface.

     

    You don't mention which version of the Vivado tools you are using, but it is the current version you could build a basic AXI BRAM Controller and let the 'Run Connection Automation' option build a basic BRAM example for you to compare to your implementation. You will need to provide a clock and a reset. For a test you could enable FCLK_CLK0 and set to 50 MHz. Make sure that your Zynq processing system has a master AXI interface enabled. Then add an AXI_BRAM_Controller to your block diagram. Then 'Run Connection Automation' and let the system make the required connections for you. Test the result and compare to your implementation.

     

    -Gary