I have a problem that I am trying to fix in a program I have written.
I receive internet packets, the Rx interrupt affects a bool so that in a loop I can to to then request the RxBD from the hardware. I then copy out the packets into some linked list containers that I have before returning the BDs to the hardware.
My problem is that when I go to read the data that the BD points to, the cached data is wrong, so I invalidate it. Except that using
void Xil_DCacheInvalidateRange(unsigned int adr, unsigned len)
invalidates a cache line but not necessarily where the packet information starts. It looks at the address I pass to it, then it moves from there to the start of the first cache line and only then begins invalidating the cache.
This leads to varying parts of my packet information being "chopped off". Anywhere from 0 to 28 bytes worth of data.
A solution to this, as stated in the Xilinxs documentation seems to be to cache align the... sections of memory that the BD point to. The problem is, I have no idea how to do this.
I have tried simply disabling the entire cache at the start of the program, however this doesn't seem to work. I don't know if it is my attempt that doesn't work, or if it simply doesn't fix the problem.
(Code used to try to disable the entire cache)
Xil_L2CacheDisable();
Xil_L1DCacheDisable();
Xil_L1ICacheDisable();
dsb();
isb();
