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Keep PL configuration after PS reset

Former Member

Hello,

I need to keep the configuration of the PL when I reset my Application/OS. I would like to create an FSBL with the next behavior:

1. Initialize everything, but PL.
2. Check the PL configured flag.
   2a. Configure the PL if it is not configured yet.
   2b. If the PL is configured do not reset it, skip the configuration phase.
3. Load App/Os and execute it.

I am trying to modify the default FSBL; I have detected that after MIO initialization the "Done" led of the FPGA is turned off.

I cannot get any reference of this behavior.


It possible the behavior that I want?

Thanks a lot,
Jonathan.

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    Hi Jonathan,

    I checked with our top expert in this area, and he confirms that Gary is absolutely correct when you are using the standard FSBL generated by the Xilinx tools.  However, the FSBL source code is available in the SDK, and hence is fully customizable.   Here's what he said:

    "I believe it’s true if standard FSBL is used. However, FSBL can be modified not to reconfigure the PL on reset (have not tried this). Doing this would require some care as the PS signals going to the PL will change state as soon as PS is reset. So, somehow the PL needs to be held in reset (not reconfigured, just reset) during PS reset."

    In addition, you may be able to improve your load times by providing an initialization file as part of the boot.bin.  This allows various PS registers to be set to optimized values prior to any files being loaded from their permanent locations.   Details on this and pointers to additional information can be found in the Zynq Boot course in the most recent X-fest.

    http://www.xfest2014.com/

    It may take a little work on your part, but what you want to do should be possible.  If you decide to pursue this, please let us know how it goes.  

    Ron

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  • 0

    Hi Jonathan,

    I checked with our top expert in this area, and he confirms that Gary is absolutely correct when you are using the standard FSBL generated by the Xilinx tools.  However, the FSBL source code is available in the SDK, and hence is fully customizable.   Here's what he said:

    "I believe it’s true if standard FSBL is used. However, FSBL can be modified not to reconfigure the PL on reset (have not tried this). Doing this would require some care as the PS signals going to the PL will change state as soon as PS is reset. So, somehow the PL needs to be held in reset (not reconfigured, just reset) during PS reset."

    In addition, you may be able to improve your load times by providing an initialization file as part of the boot.bin.  This allows various PS registers to be set to optimized values prior to any files being loaded from their permanent locations.   Details on this and pointers to additional information can be found in the Zynq Boot course in the most recent X-fest.

    http://www.xfest2014.com/

    It may take a little work on your part, but what you want to do should be possible.  If you decide to pursue this, please let us know how it goes.  

    Ron

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