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Software Application Development Keep PL configuration after PS reset
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Related

Keep PL configuration after PS reset

Former Member
Former Member over 9 years ago

Hello,

I need to keep the configuration of the PL when I reset my Application/OS. I would like to create an FSBL with the next behavior:

1. Initialize everything, but PL.
2. Check the PL configured flag.
   2a. Configure the PL if it is not configured yet.
   2b. If the PL is configured do not reset it, skip the configuration phase.
3. Load App/Os and execute it.

I am trying to modify the default FSBL; I have detected that after MIO initialization the "Done" led of the FPGA is turned off.

I cannot get any reference of this behavior.


It possible the behavior that I want?

Thanks a lot,
Jonathan.

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  • Former Member
    0 Former Member over 9 years ago

    Hello Jonathan,

     

    Any reset that would initiate a boot sequence will also reset the PL and will require a reconfiguration.

     

    Take a look a the Zynq Technical Reference Manual (UG585), particularly chapter 2 and chapter 26:

     http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago

    Hello Jonathan,

     

    Any reset that would initiate a boot sequence will also reset the PL and will require a reconfiguration.

     

    Take a look a the Zynq Technical Reference Manual (UG585), particularly chapter 2 and chapter 26:

     http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

     

    -Gary

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  • Former Member
    0 Former Member over 9 years ago in reply to Former Member

    It is a problem for me. The configuration of the PL needs around 5 seconds.

    Thanks you!

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