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wl18xx driver configuration for MicroZed

Former Member

Hello, we are currently integrating a Wilink8 moule within our system, which is based on a MicroZed and a custom carrier card.

We can get the module up and running using the PB-AES-PMOD-WILINK8-G-V5 adapter board, and the MicroZed I/O Carrier Card, essentially the demo configuration. H

owever, the enable lines for bluetooth and wifi, as well as the wifi_irq line are routed through the PL on OUR system, not MIO, which is what the example driver is configured for.

More importantly, wifi enable and wlan_irq, in the example, use GPIO bank 0 which cannot be routed to the PL as per the Zynq TRM.

How do we configure the driver to use GPIO bank 2 (EMIO) for these lines (wifi enable, and wlan_irq)? TI's website didn't provide too much information on the matter.

Tom

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    Tom

    Routing of the relatively high-speed WLAN SDIO interface via the PL fabric and EMIO pins is quite a bit more challenging and I would caution against using this approach if at all possible! (The many comments on Xilinx forums on this topic are an indicator of what other users have run into when implementing this...)  

    Having said this, here are a coupleve pointers to help should you wish to proceed with this approach:

    1) Refer to chapter 13 of UG585 (Zynq TRM) to get familar with the SDIO interface as implemented via EMIO.

    2) Clocking of the WLAN SDIO interface must be reduced from 50MHz to 25MHz.

    3) A feedback clock input (EMIOSDIO1CLKFB) now needs to be connected, ideally this would be fed-back from outside the Zynq device but if the PCB routing distance is short this can be fed-back at Zynq's IO pins internally.

    4) In your IP Integrator design entry you will need to add "Fabric Interrupts", enable the PL to PS Interrupt port and connect it accordingly in your block diagram.

    5) Bindings in the Linux device tree .DTS file will need to be changed accordingly

    6) Pinout and timing constraints will need to be added for the SDIO interface to your Vivado design.

    Regards
    Peter

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    Thanks M for your response. The basic SDIO interface (D0-3, MODE, CLK) is routed through the MIO on my design, going straight to the interface, and my kernel can see the device and so forth. Its just the 2 GPIO lines that the WLAN driver specifically needs (EN, and IRQ) that need to be run through the PL on my design. Its more, how do I configure GPIO Bank 2 (EMIO) and the deivce tree to perform the same functionality as MIO0 and MIO9 in the reference implementation.

    Tom

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    Jason

    Not yet verified with hardware but here's what I understand is needed in context of your 2 questions:

    1) How to configure the two GPIOs (WL_EN, and WL_IRQ) to use GPIO Bank 2? (EMIO)

    By way of example, assume this a Wi-Fi only system and that:
    a) no other EMIO GPIO is used in your system
    b) the following Pmod-JE pinout on IO Carrier Card is used to implement these 2 signals using IO Bank35 EMIO:
    WL_EN  = Pmod_JE_pin1 (Pkg pin: E17, Zync pin: IO_L3P_T0_DQS_AD1P_35) 
    WL_IRQ = Pmod_JE_pin2 (Pkg pin: E18, Zync pin: IO_L3N_T0_DQS_AD1N_35)

    In IP Integrator, Re-Customize IP (processing_system7_0):
    WL_EN:
    Under MIO Configuration / IO Peripherals / GPIO:
    - Select EMIO GPIO (Width)
    - Increase width to 1 to accommodate the WL_EN EMIO output pin 

    WL_IRQ:
    In IP Integrator, under Interrupts:
    - Select Fabric Interrupts   
    - Select IRQ_F2P[15:0]
    - More on this topic here:
    http://forums.xilinx.com/t5/Xcell-Daily-Blog/Adam-Taylor-s-MicroZed-Chronicles-Part-38-Answering-a-question/ba-p/479978

    In IP Integrator, wire-up the block-diagram:
    WL_EN : needs to be wired to GPIO_0 output pin
    WL_IRQ: needs to be wired to In3 of a Concat wired to IRQ_F2P[3:0]

    In the WL8_constraints.xdc file, add the following constraints:
    set_property PACKAGE_PIN E17 [get_ports WL_EN];    # WL_EN
    set_property IOSTANDARD LVCMOS33 [get_ports BT*];  # IO voltage=3.3V
    set_property PACKAGE_PIN E18 [get_ports WL_IRQ];   # WL_IRQ
    set_property IOSTANDARD LVCMOS33 [get_ports BT*];  # IO voltage=3.3V


    2) What changes are needed in the Linux DTS bindings to achieve same functionality? (as MIO0 and MIO9 in ref design):
    - Change the following sections of your DTS file and then regenerate the DTB device tree binary

    wlcore {
        compatible = "wlcore";
        interrupt-parent = <&ps7_scugic_0>;
        irq = <91>;            /* WL_IRQ moved to EMIO for IRQ_F2P interrupt input */ 
        platform-quirks = <1>; /* use edge irqs for suspend/resume */
        board-ref-clock = <4>; /* if a 12xx card is there, configure the clock to WL12XX_REFCLOCK_38_XTAL */
    };

    wlan_en_reg: fixedregulator@1 {
        compatible = "regulator-fixed";
        regulator-name = "wlan-en-regulator";
        regulator-min-microvolt = <3300000>; /* Actually 1.8V, but this keeps the driver happy */
        regulator-max-microvolt = <3300000>;
        gpio = <&ps7_gpio_0 54 0x4>;         /* WL_EN moved to EMIO for PL Pmod_JE_pin1, IO Bank 35*/
        startup-delay-us = <70000>;          /* WLAN card specific delay */
        enable-active-high;
    };