Actions
Forum Thread Details
  • State Not Answered
  • Replies 1 reply
  • Subscribers 328 subscribers
  • Views 597 views
  • Users 0 members are here
Related

Explanation of Zynq ICCPMR, ICDIPR, ICCIAR registers?

henry10210

I actually just posted this question to Xilinx forum, so I feel guilty about double-posting; it's just that Xilinx support responsiveness has gone to sh*t at about the time they stopped taking webcase.  I thought highly of Xilinx support before, but I think they are now on-par with or perhaps worse than Altera.  On the contrary, this forum is much better, so I am trying my luck here--please pardon me.

I just got a A9 private timer interrupt working on a Zedboard, based on the example code generated from the BSP documentation page.  There are couple of parts that do NOT make sense to me.  If will explain how I think it works (apparently, it does); if someone can point out where my understand is incomplete/wrong, I'd appreciate it.

The GIC is quite configurable, and can handle 96 independent interrupt sources identified with an interrupt ID.  The private timer interrupt, for example is 29.  I read this in the SCU private timer section of the Zynq TRM.  But the TRM does not have a table of all 96 interrupt sources; so I find that I have to read the TRM carefully to tease out the IDs.  The global timer ID seems to be 27, based on the explanation of the Global_Timer_Control_Register.  Likewise, the watchdog is ID 30.

Is the lack of a definitive interrupt ID table because Zynq allows the SW to set the interrupt ID of different sources?  If so, how does one do that?  Or is this just baked into the HW in Vivado?

Next: I do NOT understand the interrupt priority.  The purpose of ICCPMR (8 bit) is to shielf the processor from uninteresting interrupts.  Since ICDIP[23:0] is 3 bytes, it suggests that I can change the priority of each of the 96 interrupts.  But the XSDK generated example is unclear.  It sets the ICCPMR t0 0xF0, but does NOT set the ICDIP register, which would mean that the PoR priority of private timer interrupt (ID 29) is greater than 0xF0--contrary to the TRM (which says it is 0).  Like I said, the example works; I just don't understand how it works.  At the moment, I could not even think of a reason for not leaving the ICCPMR at the PoR setting (0)--the example still works.

Thank you very much for reading (and hopefully answering) my question.

Parents
  • 0

    Hi Henry,

    The GIC is a complicated and highly configurable controller.  Hopefully I can help you answer some of your questions by pointing out some additional resources to help explain GIC behavior.

    First of all, there have been some recent updates to the TRM.  I don't track them closely enough to know if any changes to the interrupt sections are made, but the latest version I am looking at is v1.10 from here:

    http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

    There are three categories of interrupts that the GIC handles and their relationships are shown in Figure 7-1 of the TRM.

    1) The Software Generated Interrupts (SGI) are able to be assigned to a particular CPU or routed to additional CPU cores.  These are shown in Table 7-2 and cover interrupt numbers 0:16.

    2) There are a set of Private Peripheral Interrupts (PPI) that are connected to each CPU core and fixed and cannot be changed.  These are shown in Table 7-3 and cover interrupt numbers 16:31.

    3) The Shared Peripheral Interrupts (SPI) can also be routed to one or both CPUs.  These are shown in Table 7-4 and most of these have sources which cannot be changed and cover interrupt numbers 32:95.  Two special set of these exist PL[0:7] and PL[8:15] which Vivado is able to connect up to programmable logic resources to allow flexibility with additional interrupt sources beyond what is already connected to the CPU from internal hard peripheral controllers.

    The TRM does offer a high level overview of Interrupt Prioritization in section 7.4.1 but the underlying configuration and control is rather complex.  Due to the complexity of the behavior, I think the TRM has to be limited in the amount of information presented here simply because going deeper would then be going into an area that is re-documenting the PL390 behavior.  There is another document from ARM that offers a much more thorough explanation of the GIC (PL390) architecture that you might find useful.

    I suggest searching for the following two documents on the ARM website (both will require an ARM customer login) which provide more information on the GIC:

    IHI0048B - ARMu00AE Generic Interrupt Controller - Architecture Specification

    DDI0416B - PrimeCellu00AE Generic Interrupt Controller (PL390) - Technical Reference Manual

    I know there is a lot of information within those documents (I won't pretend to understand all of the detailed GIC behavior myself) but it seems like you are reaching that level complexity in your code where you need to understand the programming model for the GIC at a deeper level than offered in the TRM.

    Regards,

    -Kevin

Reply
  • 0

    Hi Henry,

    The GIC is a complicated and highly configurable controller.  Hopefully I can help you answer some of your questions by pointing out some additional resources to help explain GIC behavior.

    First of all, there have been some recent updates to the TRM.  I don't track them closely enough to know if any changes to the interrupt sections are made, but the latest version I am looking at is v1.10 from here:

    http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf

    There are three categories of interrupts that the GIC handles and their relationships are shown in Figure 7-1 of the TRM.

    1) The Software Generated Interrupts (SGI) are able to be assigned to a particular CPU or routed to additional CPU cores.  These are shown in Table 7-2 and cover interrupt numbers 0:16.

    2) There are a set of Private Peripheral Interrupts (PPI) that are connected to each CPU core and fixed and cannot be changed.  These are shown in Table 7-3 and cover interrupt numbers 16:31.

    3) The Shared Peripheral Interrupts (SPI) can also be routed to one or both CPUs.  These are shown in Table 7-4 and most of these have sources which cannot be changed and cover interrupt numbers 32:95.  Two special set of these exist PL[0:7] and PL[8:15] which Vivado is able to connect up to programmable logic resources to allow flexibility with additional interrupt sources beyond what is already connected to the CPU from internal hard peripheral controllers.

    The TRM does offer a high level overview of Interrupt Prioritization in section 7.4.1 but the underlying configuration and control is rather complex.  Due to the complexity of the behavior, I think the TRM has to be limited in the amount of information presented here simply because going deeper would then be going into an area that is re-documenting the PL390 behavior.  There is another document from ARM that offers a much more thorough explanation of the GIC (PL390) architecture that you might find useful.

    I suggest searching for the following two documents on the ARM website (both will require an ARM customer login) which provide more information on the GIC:

    IHI0048B - ARMu00AE Generic Interrupt Controller - Architecture Specification

    DDI0416B - PrimeCellu00AE Generic Interrupt Controller (PL390) - Technical Reference Manual

    I know there is a lot of information within those documents (I won't pretend to understand all of the detailed GIC behavior myself) but it seems like you are reaching that level complexity in your code where you need to understand the programming model for the GIC at a deeper level than offered in the TRM.

    Regards,

    -Kevin

Children
No Data