triple frame buffer

Question

Hello

I have an application that uses the VDMA core for transferring video from camera IP to DDR on a Zynq 7020 (bare metal application). I am using the default number of frame buffers (3). My application uses interrupts to notify when a frame buffer transfer has completed. I have setup the VDMA driver for circular buffer mode. I read the buffers from DDR in the following order 0,1,2,0,1,2... (Normal circular buffer processing) when an interrupt fires. When I look at the images, the first cycle through all the buffers looks good. After the first cycle buffer 0 stays the same and only buffer 1 and 2 change. I'm not sure if I understand now what triple buffering means in the VDMA context. Is it not just a simple ring buffer that constantly cycles though the buffers in the order 0-1-2.

Kevin

kcox@sgss.com · Accepted Answer

I fixed the problem by disabling the read channel in the VDMA core. I am working with a reference design that used both the read and write channels of the VDMA core. I modified the design and removed the connections from the M_AXIS_MM2S port so that the DMA core was no longer outputting data to the HDMI logic. But I did not check the box in the DMA core that disables the read channel. This must cause confusion internal to the DMA core as I also had the GenLock logic activated that keeps the read and write channels in sync.