Hi,
I've currently running a bare metal application on each core of my ZedBoard. I would like to split up the L2 cache so both cores can use it via lockdown by master. The register detail section of the Zynq 7000 TRM indicates that the L2 cache controller uses 8 different ways, and I've ensured that "pl310_LOCKDOWN_BY_MASTER" was defined by reading the "reg0_cache_type" register.
I've setup the "reg9_d_lockdown0" and "reg9_i_lockdown0" registers to 0x0000_00AA and the "reg9_d_lockdown1" and "reg9_i_lockdown1" registers to 0x0000_0055 so that CPU0 will use ways 0, 2, 4, and 6 while CPU1 uses ways 1, 3, 5, and 7.
The part I don't understand is how to drive the AyUSERSx[7:5] signal. I know that it needs to be set so that AyUSERSx[7:5] = {1'b0, AyIDMx[1:0]}, since AyIDMx[1:0] will be b00 for CPU0 and b01 for CPU1. I just don't know how to set that.
If anyone could point me in the right direction, the help would be greatly appreciated!
